Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2000-05-02
2002-10-15
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S690000, C438S697000, C438S700000, C438S706000, C438S745000
Reexamination Certificate
active
06465351
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 99-15923, filed on May 3, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a capacitor that can skip a CMP process with respect to an uneven interlayer insulating layer underlying a sacrificial oxide layer in which the capacitor is to be made.
An integrated circuit DRAM device typically includes many memory cells. In fact, a memory cell is provided for each bit stored by the DRAM device. Each individual memory cell typically consists of a storage capacitor and an access transistor. Either the source or the drain of the access transistor is connected to one terminal of the storage capacitor. The other side of the transistor's channel and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage.
The formation of a DRAM memory cell includes the formation of a transistor, of a capacitor, and of contacts to external circuits. The capacitor types that have been typically used in DRAM memory cells are planar capacitors, because they are relatively simple to manufacture.
However, in order to fabricate high density DRAM devices, the memory cells must be scaled down in size to the sub-micrometer range. This causes a reduction in capacitor area, resulting in the reduction of the cell capacitance. In this case, because the area of the charge storage capacitor is also decreased, the capacitance of the planar capacitor becomes relatively small. This decreases in storage capacitor leads to lowered signal-to-noise ratios and increased errors due to alpha particle interference. Accordingly, for very small memory cells, planar capacitors become unreliable.
In addition, as the capacitance decreases, the charge held by the storage capacitor must be refreshed more often, further degrading performance. A simple planar capacitor generally cannot provide sufficient capacitance for good performance, even with high performance dielectrics, such as Ta
2
O
5
.
Prior approaches to overcoming these problems have resulted in the development of the trench capacitor (see for example, U.S. Pat. No. 5,374,580) and the stacked capacitor (see for example, U.S. Pat. No. 5,021,357). Trench capacitors experience the well-known problem of “gate diode leakage.” Accordingly, stacked capacitors have been more widely fabricated recently.
For example, U.S. Pat. Nos. 5,763,304, 5,668,036, and 5,717,236, the disclosures of which are incorporated herein by reference, disclose a stacked capacitor that uses a chemical mechanical polishing (CMP) step with respect to an interlayer insulating layer on which the stacked capacitor is formed. In the conventional methods, a CMP process is carried out on the interlayer insulating layer because of its uneven surface topography. In a subsequent process, the CMP process is also carried out to electrically separate each storage node from one another.
As is well known, the CMP process suffers from the disadvantages of high expense, low throughput, process complexity, and high defect density. Accordingly, it would be very desirable to provide a method for fabricating a capacitor that can minimize the number of CMP processes required.
SUMMARY OF THE INVENTION
The present invention was made in view of the above problems, and is directed toward providing a method for fabricating a stacked capacitor that can minimize the use of CMP processes. In particular, the present invention omits a CMP process with respect to an interlayer insulating layer, but avoids causing problems mentioned above.
One of the features of the present invention is the formation of a CMP stopping layer on a sacrificial oxide layer to serve for CMP end point detection. Such a CMP stopping layer can make it possible to omit a CMP process with respect to the interlayer insulating layer.
Briefly, an interlayer insulating layer is formed over an integrated circuit substrate having undergone certain process steps, such as defining active and inactive regions, formation of transistors and formation of bit lines. Since transistors and bit lines are formed densely in the cell array region, and are formed sparsely in the peripheral region, there can arise a height difference (i.e., causing a step portion) in the surface of the interlayer insulating layer at the peripheral region. The interlayer insulating layer is preferably made of an oxide material selected from the group consisting of borophosphosilicate glass (BPSG) and undoped silicate glass (USG). More particularly, if a BPSG layer is formed, it is done so by the process of first depositing the BPSG, and then reflowing it at a predetermined temperature to provide a good surface topology.
Since conductive patterns are formed densely on the cell array region, the interlayer insulating layer has a substantially even surface over the cell array region. On the other hand, since conductive patterns are formed sparsely in the peripheral region, the interlayer insulating layer has an uneven surface topology over the peripheral region, i.e., it contains a step.
Contact plugs are then formed in the interlayer insulating layer. The contact plugs are electrically connected to the integrated circuit substrate. Unlike in the conventional method, a CMP process is not carried out on the interlayer insulating layer.
A sacrificial oxide layer is then deposited over the interlayer insulating layer, following the topography of the interlayer insulating layer. The sacrificial oxide layer is formed to a thickness at least the desired height of the storage node. This sacrificial oxide layer comprises an oxide material selected from the group consisting of BPSG, USG, phosphosilicate glass (PSG), spin on glass (SOG), hydrogen silsesquioxane (HSQ), and plasma enhanced tetraethylorthosilicate (PE-TEOS).
A CMP stopper layer is then formed over the sacrificial oxide layer, following the topography of the sacrificial oxide layer. The CMP stopper layer preferably comprises a material selected from the group consisting of silicon nitride, an alumina, a diamond-like carbon, aluminum nitride, and boron nitride. A second oxide layer may also be formed over the CMP stopping layer to provide a wide process margin for subsequent CMP processes.
Through photolithographic process, the second oxide layer, the CMP stopping layer, and the sacrificial oxide layer are etched to form trenches that expose the contact plugs. A conductive material, for the formation of the storage nodes, is then deposited in the trenches and over the second oxide layer. A CMP process is then carried out using the CMP stopping layer as an end point, to thereby form a storage node in the trench. The CMP stopping layer and any portions of the second oxide layer remaining over the CMP stopping layer at the lower portion of the step are then removed.
In method mentioned above, an etching stopper layer can also be formed prior to the formation of the sacrificial oxide layer. More specifically, after the formation of the contact plugs, an etching stopper layer, comprised of a nitride, may be deposited on interlayer insulating layer and the contact plugs. Alternately, the etching stopper layer can be formed formed on the interlayer insulating layer prior to the formation of the contact plugs. This etching stopper can allow a wide process margin during the formation of the trenches in the sacrificial oxide layer. Also, this etching stopper layer serves to increase capacitor area.
After removing the CMP stopping layer and any remaining second oxide layer, the sacrificial oxide layer outside the storage nodes is removed. In case that the etching stopper is formed on the interlayer insulating layer, it can be removed subsequent to the removal of the sacrificial oxide layer.
The method may also comprise forming a hemispherical grain (HSG) silicon layer
Perez-Ramos Vaness
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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