Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-02-08
2002-08-06
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06430732
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to hardware description languages (HDLs), and more particularly to template-based layout specification using constructs generally provided by the languages.
BACKGROUND OF THE INVENTION
Field programmable gate arrays (FPGAs), first introduced by Xilinx, Inc. in the 1980's, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate, because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability. One such FPGA, the Xilinx XC4000™ Series FPGA, is described in detail in pages 4-5 through 4-69 of the Xilinx 1998 Data Book entitled “The Programmable Logic Data Book 1998”, published in 1998 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
As FPGA designs increase in complexity, they reach a point at which the designer cannot deal with the entire design at the gate level. Where once a typical FPGA design comprised perhaps 5,000 gates, FPGA designs with 50,000 gates are now common, and FPGAs supporting over 300,000 gates are available. To deal with this complexity, circuits are typically partitioned into smaller circuits that are more easily handled. Often, these smaller circuits are divided into yet smaller circuits, imposing on the design a multi-level hierarchy of logical blocks.
Libraries of pre-developed blocks of logic have been developed that can be included in an FPGA design. Such library modules include, for example, adders, multipliers, filters, and other arithmetic and DSP functions from which complex designs can be readily constructed. The use of pre-developed logic blocks permits faster design cycles by eliminating the redesign of circuits. Thus, using blocks of logic from a library may reduce design costs. However, the circuit that results when combining predefined logic blocks may have sub-optimal circuit performance.
Many high-performance FPGA circuits require customized layouts to achieve required performance levels. However, present methods are not particularly conducive to convenient, error-free specification of layouts. For example, module floorplans can be specified with component placement constraints that are x, y, and s coordinates, where x and y are either constants or arithmetic expressions, and s is a device site such as a particular lookup table. However, determining and maintaining these expressions for complex floorplans can be difficult and error-prone, particularly when the modules are hierarchical.
A method that address the aforementioned problems, as well as other related problems, is therefore desirable.
SUMMARY OF THE INVENTION
In various embodiments, the invention provides a method for structured layout of design objects in a hardware description language (HDL). The present method provides placement directives that use standard features of the HDL instead of special extensions to the HDL or comment-based placement annotations. Thus, the placement directives are compatible with any tool adhering to the HDL specification. In addition, the placement directives do not require coordinate-based specification of design objects, thereby alleviating the involved and error-prone specification and maintenance of coordinates for a complex hierarchical design.
In accordance with one embodiment, a method is provided for structured layout of design objects in a hardware description language (HDL). Standard features of the HDL are used to specify a first-level design object and placement of other design objects within the first-level design object. A first-level design object is declared, wherein the first-level design object has no input or output ports and has one or more slots available for one or more second-level design objects. Values are assigned to attributes of the first-level design object to indicate placement for the second-level design objects within the first-level design object. The second-level design objects are declared as elements within the first-level design object, and the first and second-level design objects are thereafter compiled.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.
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Hwang L. James
Mitra Sujoy
Patterson Cameron D.
Maunu LeRoy D.
Smith Matthew
Thompson A. M.
Xilinx , Inc.
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