Signal generation circuit of semiconductor testing apparatus

Details Signal generation circuit of semiconductor testing apparatus Signal generation circuit of semiconductor testing apparatus

2000-05-22

2002-11-05

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

Reexamination Certificate

active

06477668

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a signal generation circuit of a semiconductor testing apparatus, and particularly to a signal generation circuit provided with a skew correction function.
Conventionally, a semiconductor testing apparatus to test a semiconductor memory, has a signal generation circuit to generate a plurality of channel signals, and the signal generation circuit is composed of a plurality of format channels to generate signals according to a program in which testing procedure is written. The format channel is provided for each signal channel, and by composing a plurality of timing edges, generates a set-edge and reset-edge signals which regulate signals to be applied onto an object to be tested.
Herein, in the testing apparatus, because the transmission path of each timing edge signal is not necessarily the same, there is a skew between respective signals before composition, and signals are not applied on the testing object at the designated timing by the program. Therefore, in the signal generation circuit of the semiconductor testing apparatus, a skew correction circuit to correct the skew between respective signals before composition, is provided.
In
FIG. 5
, the structure of the conventional signal generation circuit of the semiconductor testing apparatus is shown. In the drawing, numerals
1
and
2
are format channels, numeral
61
and
62
are logical add circuits to conduct the logical add of each of outputs of two format channels
1
and
2
. Herein, the format channel
1
is structured by: clock selection circuits
11
to
13
which receive a plurality of timing edge signals from a timing generation section, not shown, and select one of them; a formatter circuit
21
to separate the output edge of the clock selection circuits
11
to
13
into a set-edge or a reset-edge; skew correction circuits
31
to
34
to correct the timing of the set-edge or reset-edge outputted from the formatter circuit
21
; and logical add circuits
41
and
42
to conduct the logical add of respective set-edge and reset-edge whose skews are corrected.
Another format channel
2
is structured in the same manner as the format channel
1
, and structured by: clock selection circuits
14
to
16
corresponding to clock selection circuits
11
to
13
; a formatter circuit
22
corresponding to the formatter circuit
21
; skew correction circuits
35
to
38
corresponding to skew correction circuits
31
to
34
; and logical add circuits
43
and
44
corresponding to logical add circuits
41
and
42
.
Next, operations of the signal generation circuit will be described. Initially, concerning a case of a normal mode in which separate signal s are generate d by each format channel, the format channel
1
will be described as an example.
The clock selection circuits
11
to
13
select one of timing edges described in a program for the tested device measurement from a plurality of timing edges generated from the timing generation section, not shown, and respectively output and supply it to the formatter circuit
21
.
The formatter circuit
21
separates the edge signal inputted from each clock selection circuit into the set-edge and the reset-edge so that the waveform designated by the program can be applied onto the device. The set-edge and the reset-edge determine, for example, a rise timing and a fall timing of an address signal, and regulate the timing of each edge of the signal applied onto the tested device. When the formatter circuit
21
separates the edge signal from each clock selection circuit as the set-edge, the formatter circuit
21
outputs it to the logical add circuit
41
, and when the formatter circuit
21
separates the edge signal from each clock selection circuit as the reset-edge, the formatter circuit
21
outputs it to the logical add circuit
42
.
The skew correction circuits
31
to
34
correct the skew between signals inputted into logical add circuits
41
and
42
. Concretely, the skew correction circuits
31
and
32
correct the set-edges respectively outputted from the formatter circuit
21
to the logical add circuit
41
according to the timing edge from the clock selection circuits
11
and
13
, so that the same timing as that of the set-edge outputted from the formatter circuit
21
to the logical add circuit
41
can be obtained, according to the timing edge from the clock selection circuit
12
. According to this, each set-edge is inputted into the logical add circuit
41
at the same timing.
Further, in the same manner, the skew correction circuits
33
and
34
correct the reset-edge outputted from the formatter circuit
21
to the logical add circuit
42
according to the timing edge from the clock selection circuits
11
and
13
, so that the same timing can be obtained as the reset-edge outputted to the logical add circuit
42
, according to the timing edge from the clock selection circuit
12
. According to this, each set-edge is inputted into the logical add circuit
42
at the same timing.
The logical add circuit
41
conducts the logical add of each of set-edges separated by the formatter circuit
21
, and composes them. That is, the logical add circuit
41
outputs a signal in which each set-edge outputted from the formatter circuit
21
is arranged. In the same manner, the logical add circuit
42
conducts the logical add of each of reset-edges separated by the formatter circuit
21
, and composes them, and outputs a signal in which each set-edge is arranged.
The format channel
2
is operated in the same manner as the format channel
1
, and respectively outputs a signal in which the set-edge is arranged to the channel to which the format channel
2
is allocated, and a signal in which the reset-edge is arranged, from the logical add circuits
43
and
44
.
Incidentally, in this operation mode, signals of each format channel are not composed, and because channel signals corresponding to the output signals of each format channel are generated, the logical add circuits
61
and
62
which attribute to the signal composition, do not function. Accordingly, the operation of the logical add circuits
61
and
62
will be described in the next operation of a link mode.
Next, the operation of the link mode by which each format channel is linked and a signal is generated, will be described.
In this operation mode, both of the set-edges of the format channels
1
and
2
are composed by the logical add operation by the logical add circuit
61
, and both of the reset-edges are composed by the logical add operation by the logical add circuit
62
. That is, in this operation mode, one set signal in which both of each set-edge generated by the format channels
1
and
2
are arranged, is outputted from the logical add circuit
61
, and one reset signal in which both of each reset-edge generated by the format channels
1
and
2
are arranged, is outputted from the logical add circuit
62
. In this manner, according to this link mode, because apparently 2 time edges can be arranged on one signal, this mode can cope with the high speed device with high operation frequency.
Herein, when the skew between signals outputted from each of format channels is corrected in this link mode, for example, the output from the format channel
2
is corrected so that this output is outputted from the logical add circuit
61
at the same timing as the output of the format channel
1
by using the skew correction circuits
35
to
38
.
Incidentally, according to the above-described conventional signal generation circuit, because the skew correction circuits
35
to
38
to correct the output of the format channel
2
at the time of the link mode, are also the circuits used at the time of the normal mode, there is a problem that, every time when the link mode and the normal mode are switched, it is necessary to send again the correction data appropriate for each mode to the skew correction circuits
35
to
38
.
Further, in the link mode, because any one of skew correction circuits of
2
format channels is used and the skew correc

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