Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-10
2002-12-10
Wong, Don (Department: 2821)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
36
Reexamination Certificate
active
06493865
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the semiconductor technology field. More specifically, the present invention relates to a process for producing masks for the fabrication of semiconductor structures, in which the production of a mask is carried out using layout data which contains information for defining a mask layout having individual geometric structure elements.
In the area of the fabrication of semiconductor structures, for example during the production of integrated circuits based on semiconductor wafers, a large number of individual areas, for example conductor tracks, are subdivided onto the semiconductor wafers. This structuring is carried out with the aid of the lithographic technique in which, in particular, masks or mask structures are generated which are used for the production of semiconductor structures belonging to the integrated circuit in subsequent process steps. During the production of masks or mask structures, the main objective consists in particular in generating a large number of structures on the semiconductor wafer true to size, in correct positions and without defects.
The continuous decrease in the dimensions in the production of integrated circuits increasingly demands auxiliary structures, as they are known, or modifications of the mask structures generated during the drafting of the respective mask, in order that the feasibility of producing the mask to be produced is ensured. Auxiliary structures are used, for example, for planarization. They are electrically non-active and, at the same time, permit a certain amount of geometric freedom in drafting the corresponding mask structure. Examples of technological advantages which are achieved by the modification of mask structures are improvements in the imaging properties, enlargement of the process window (process window as a general term for the admissible scatter of process parameters), improvements in the planarization properties, increases in yield or more robust designs.
In processes for producing masks, the production of a mask is usually carried out using generated layout data which contains information for defining a mask layout. In this case, the mask layout has individual geometric structure elements, which represent the mask structures. It is often the case, during the generation of the layout data, that the generation of a number of mask levels is necessary in order to optimize the fabrication process.
With the increasing complexity of the mask layout or of the layout data about a mask to be produced, and given the decrease in the dimensions, it becomes more difficult and more time-consuming to carry out modifications to the mask structures or the layout data during the mask generation, for example manually, in order that the feasibility of production of the mask is ensured. At the same time, generation errors in layout data are to be eliminated. For this purpose, it is necessary to perform technology-dependent optimization of the layout data.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of producing masks for the fabrication of semiconductor structures which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and wherein the modification of generated layout data about a mask to be produced is carried out in order to eliminate generation errors, so that the feasibility of producing the mask is ensured and which permits relatively quick modification of the layout data and its technology-dependent optimization.
With the above and other objects in view there is provided, in accordance with the invention, a method of producing masks for fabricating semiconductor structures, which comprises:
generating layout data with information defining a mask layout with individual geometric elements;
defining geometric design requirements and an arrangement for the individual structure elements;
checking the layout data as to whether the geometric design requirements and the arrangement for the individual structure elements are satisfied;
if the design requirements are not satisfied, locating corresponding error locations in the mask layout using the layout data;
generating further layout data with information for defining correction figures to correct the respective error locations; and
linking the layout data with the further layout data for modifying the layout data.
In accordance with an added feature of the invention, the further layout data are generated by modifying the layout data at the respective error locations.
In accordance with an additional feature of the invention, the layout data are generated for a single mask level or for a plurality of mask levels, and performing the method for each of the mask levels.
In sum, the above objects are achieved by a process for producing masks for the fabrication of semiconductor structures, in which the production of a mask is carried out using layout data which contains information for defining a mask layout which has individual geometric structure elements. The novel method includes the following steps:
layout data about a mask layout to be produced are generated;
geometric design requirements for individual structure elements and their disposition are defined;
the layout data are checked to see whether the geometric design requirements for the individual structure elements and their disposition are satisfied;
in the event that the design requirements are violated, the corresponding error locations in the mask layout are located using the layout data;
further layout data are generated which contain information for defining correction figures to correct the respective error locations; and
the layout data are linked with the further layout data so that the layout data are modified.
In order to carry out the process, use is made of the fact that the structure elements and their design requirements may be characterized by so-called situation-describing attributes. For example, isolated lines are distinguished by the attribute that, at a specific spacing, they are not adjacent structures. Structures for specific mask levels for improving the planarization properties are described by the attribute of an adequately large structure on the mask level to be planarized. Such attributes can be found and classified using software for physical verification (for example “Vampire”). These classified attributes are also referred to as “markers”. These markers are then used to modify the layout data as a function of the situation.
As described in the introductory text above, during the generation of layout data about a mask to be produced, generation errors are produced because of higher and higher requirements relating to the production of integrated circuits, and said generation errors violate defined design requirements. Such generation errors are, for example, violations of the spacing or width of the structure elements of the mask layout. Once the corresponding error locations have been located in the mask layout, they are corrected by superimposing correction figures, which are intended to have the effect of eliminating the violation of the design requirements. In this connection, it is also possible to speak of repairing a data state in the mask design by means of so-called repair figures.
The further layout data, which contain the information for defining the correction figures are therefore generated with reference back to the mask requirements. The further layout data are, for example, generated by modifying the layout data at the respective error locations. Once layout data about a mask to be produced have been generated for one or more mask levels, then the process can advantageously be carried out for each of the mask levels.
The method according to the invention permits the errors produced during the generation of the layout data about a mask to be produced to be rectified completely, fully automatically and in accordance with technologically predefined optimization criteria. At the same time, the process can be i
Fischer Werner
Ludwig Burkhard
Meyer Dirk
Thiele Jörg
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Tran Thuy Vinh
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