Reducing power consumption variability of static busses

Details Reducing power consumption variability of static busses Reducing power consumption variability of static busses

2000-10-24

2002-11-19

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S028000, C326S093000

Reexamination Certificate

active

06483348

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and more particularly, to techniques and circuits for reducing power supply droop and ground bounce oscillations.
BACKGROUND OF THE INVENTION
One of the causes of reduced on-chip power supply is a result of changes in the amount of current drawn from (or dumped to) the on-chip power supply lines. The changes in the amount of current drawn excite oscillations in the inherent inductances in the power delivery lines. These inherent inductances come mainly from the package leads and bond wires. The frequency of these oscillations depends upon a number of factors that vary from package-to-package and chip-to-chip. However, in high-performance integrated circuits, the frequency of operation may be much greater than the frequency of the oscillations on the power supplies. Accordingly, it is important that the circuits on these chips be designed to operate at the smallest voltage differential between a peak in the ground oscillation and a dip in the positive supply oscillation.
If circuits are not designed to operate at the smallest voltage differential between a peak in the ground oscillation and a dip in the positive supply oscillation, transistors may not meet their switch times and the operating frequency must be lowered. Thus, to meet frequency goals, the normal power supply voltage is increased to obtain a minimum acceptable differential between ground peaks and power supply dips. This increased operating voltage increases the integrated circuit's power dissipation. Increased power dissipation can increase the cost of several components of a system including the integrated circuit packaging, heat sink, and the system power supply. Furthermore, increasing the operating voltage tends to decrease the operating lifetime of the part thereby increasing the cost of a systems maintenance and amortized cost.
Accordingly, there is a need in the art for an apparatus and method for reducing the changes in the amount of current drawn on an integrated circuit's powers supplies.
SUMMARY OF THE INVENTION
An embodiment of the invention reduces the changes, or variability, in the amount of current drawn from, or dumped to, the power supplies of an integrated circuit. This, in turn, reduces the magnitudes of the smallest voltage differential between a peak in the ground oscillation and a dip in the positive supply oscillation. It is well adapted for fabrication on integrated circuits and can be particularly effective when used on wide, parallel, static busses.
Instances of an embodiment of the invention are connected to the wires of a bus. Each instance monitors the wire that it is connected to. If the wire switched from a logic state to another logic state during the last cycle of the bus, the invention does not consume any current. If, however, the wire has not made this switch during the last cycle of the bus, then the invention consumes an amount of current that may approximate the amount of current used to charge that wire had it switched. This makes the power less data dependent. Making the power consumption less data dependent reduces the overall variability in power consumption and that reduces the magnitude of the smallest voltage differential between a peak in the ground oscillation and a dip in the positive supply oscillation.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 6239621 (2001-05-01), Milshtein et al.
patent: 0284356 (1994-03-01), None

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