Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-18
2002-11-12
Smith, Matthew S (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06480998
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the field of semiconductor design. and more specifically to a method and apparatus for routing semiconductor nets that considers functional and delay noise during the routing process.
RELATED ART
As semiconductors operate at increasingly low cycle times and geometries become increasingly. small, functional and delay noise become more of a problem. Conventionally, noise or cross talk problems in the microprocessor design process are addressed by a cross talk analysis performed after a global or detailed routing of the nets in the chip. Following detailed routing, however, the chip layout is much less flexible. Consequently, it becomes very difficult to correct functional and delay noise problems identified after detailed routing. In turn, this may result in a longer time-to-market for the product.
It has therefore become desirable to develop a new method and system for routing nets which is noise-sensitive at earlier stages of the design process, as accomplished by the present invention.
REFERENCES:
patent: 568395 (1896-09-01), Huang
patent: 6278951 (2001-08-01), Sato
patent: 6353917 (2002-03-01), Muddu et al.
patent: 6378109 (2002-04-01), Young et al.
Bearden David R.
Blaauw David T.
Dasgupta Aurobindo
Mukherjee Pradipto
Do Thuan
Motorola Inc.
Smith Matthew S
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