Static information storage and retrieval – Read/write circuit – Sipo/piso
Reexamination Certificate
2001-04-30
2002-10-29
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Sipo/piso
C365S221000
Reexamination Certificate
active
06473352
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a link program circuit for programming an internal state of a core circuit with link elements. More particularly, the invention relates to an arrangement of programmable link elements in the semiconductor integrated circuit device.
2. Description of the Background Art
In a semiconductor integrated circuit device, a fuse program circuit (link circuit) is arranged for adjusting internal operation characteristics after manufacturing of the circuit device. By programming (blowing or no-blowing) fuse elements (link elements) in this fuse program circuit, variations in manufacturing parameters are compensated for to set the internal circuit characteristics optimum values, and further a defective bit in a storage device is repaired so that the manufacturing yield is improved. The fuse program circuit is generally referred to as an LT (Laser Trimming) link circuit because laser is generally used for programming the link elements (fuse elements).
A redundant circuit for repairing a defective bit is an example of the circuitry utilizing the LT link circuit, as is disclosed in Japanese Patent Laying-Open No. 11-31398. The defective bit repair circuit repairs a defective bit by programming a defective address with the link element to replace the circuit at the defective address with a redundant circuit. This LT link circuit is arranged for each fault repairing unit such as a row block.
The LT link circuit is used for adjusting the delay time of a delay circuit to optimize the operation timings of internal circuitry. In this case, the number of delay stages or the operation current is adjusted by programming the link elements, to adjust the timing of signals, resulting in an improved operation margin.
The semiconductor integrated circuit device produces an internal voltage for a specific internal operation from an external power supply voltage. Such internal voltages include a reference voltage defining an operation power supply current, and a reference voltage for determining the voltage level of an internal power supply voltage or an internal high voltage. When the voltage level of the reference voltage changes from a predetermined voltage level, internal operation conditions change so that intended operation characteristics cannot be achieved. For adjusting the voltage level of the reference voltage, the LT link circuit is arranged for such a circuit for generating the reference voltage.
As described above, the purpose of provision of the LT link circuit is not restricted to repairing of defective bits in the semiconductor memory device. LT link circuits are generally arranged in the semiconductor integrated circuit devices for compensating for variations in various operation conditions caused by variations in manufacturing parameters. The LT link circuit is generally arranged near a target circuit. This arrangement is employed for preventing complication of signal interconnection lines. Also, this arrangement is employed in the case of repairing defective bits, because a signal indicating use or nonuse of a redundant bit must be transmitted fast for fast repairing of the defective bits.
FIG. 57
shows an example of a structure of the conventional LT link circuit. In
FIG. 57
, an LT link circuit
1
includes: a P-channel MOS transistor (insulated gate field effect transistor)
1
a
which is connected between a power supply node NDP and an internal node ND
0
, and receives on its gate a reset signal RST_B; and a link element
1
c
and an N-channel MOS transistor
1
b
, which are connected in series between internal node ND
0
and a ground node. N-channel MOS transistor
1
b
receives reset signal RST_B on its gate.
LT link circuit
1
further includes: an inverter
1
d
which inverts a signal on internal node ND
0
, and outputs program data FDATA; and a P-channel MOS transistor
1
e
which receives program data FDATA received from inverter
1
d
on a gate thereof, and selectively couples power supply node NDP to internal node ND
0
electrically. Inverter
1
d
and MOS transistor
1
e
form a so-called half latch.
When reset signal RST_B is at L-level, MOS transistor
1
b
is off, and MOS transistor
1
a
is on, so that MOS transistor
1
a
charges internal node ND
0
to the power supply voltage level. Accordingly, inverter
1
d
drives program data FDATA to the L-level so that P-channel MOS transistor
1
e
is turned on, and inverter
1
d
and MOS transistor
1
e
latch program data FDATA.
When reset signal RST_B attains H-level, MOS transistor
1
a
is turned off, and MOS transistor
1
b
is turned on. When link element (fuse element)
1
c
is blown off, internal node ND
0
maintains H-level, and program data FDATA attains L-level. If link element
1
c
is not blown, a path for current flowing from internal node ND
0
to the ground node is present, and internal node ND
0
attains L-level, and thereby program data FDATA generated from inverter
1
d
attains H-level. In this state, MOS transistor
1
e
is off.
Accordingly, when reset signal RST_B attains H-level, program data FDATA is set to a logical level corresponding to blowing
on-blowing of link element
1
c
. This program data FDATA is applied to a target circuit or a circuit of interest in the succeeding stage for achieving an intended internal circuit operation.
FIG. 58
shows, by way of example, a structure of a circuit using the LT (laser trimming) information. In
FIG. 58
, a reference voltage generating circuit for generating a reference voltage Vref is shown as an example of an internal circuit. In
FIG. 58
, the reference voltage generating circuit includes: a constant current source CRS connected between a power supply node NDP
1
and an output node ND
1
; resistance elements R
0
-Rn connected in series between output node ND
1
and the ground node; and N-channel MOS transistors TR
1
-TRn connected in parallel to resistance elements R
1
-Rn to receive program data FDATA
1
-FDATAn on their gates, respectively.
In the reference voltage generating circuit shown in
FIG. 58
, the voltage level of reference voltage Vref depends on a resistance value between output node ND
1
and the ground node as well as a current I flowing from constant current source CRS. By selectively setting program data FDATA
1
-FDATAn to H-level or L-level by the LT link circuit, MOS transistors TR
1
-TRn are selectively turned on/off so that the resistance value between node ND
1
and the ground node is adjusted. When all MOS transistors TR
1
-TRn are made conductive, resistance elements each R
1
-Rn attain a short-circuited state, and a state is achieved equivalently that only resistance element R
0
is connected between output node ND
1
and the ground node. In this state, reference voltage Vref is at the voltage level expressed by I·R
0
, where R
0
represents a resistance value of resistance element R
0
.
When all MOS transistors TR
0
-TRn are off, the resistance value between output node ND
1
and the ground node becomes equal to (R
0
+. . . +Rn), and reference voltage Vref is at the voltage level expressed by I·R, where R represents a combined resistance of series-connected resistance elements R
0
-Rn.
Therefore, by selectively turning on/off these MOS transistors TR
1
-TRn in accordance with program data FDATA
1
-FDATAn, the voltage level of reference voltage Vref can be adjusted to the optimum level, and can be adjusted so as to optimize the internal operation.
FIG. 59
schematically shows a whole structure of a semiconductor memory device as an example of the semiconductor integrated circuit device. The semiconductor memory device shown in
FIG. 59
is an eRAM (embedded Dynamic Random Access Memory), which is integrated with a logic such as a processor on a common semiconductor chip.
In
FIG. 59
, the semiconductor memory device includes: memory cell arrays
2
a
and
2
b
each having a plurality of memory cells arranged in rows and col
Dosaka Katsumi
Nishino Aiko
Watanabe Naoya
Mitsubishi Denki & Kabushiki Kaisha
Tran M.
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