Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1998-09-29
2002-08-06
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S081000, C326S087000, C327S534000
Reexamination Certificate
active
06429684
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present application relates to a drain-to-body-tie configuration that significantly reduces gate delay and is particularly appropriate for large drivers where a series of inverters is used.
It is a well known dilemma that as supply voltages are scaled lower, CMOS threshold voltages must also be scaled lower to maintain performance, leading to increased subthreshold leakage. One solution to mitigate the trade-off between high performance and low standby current is to modulate the threshold voltage (V
t
) by control of the well or body voltage, lowering the V
t
in active mode and raising the V
t
in standby mode. Silicon-on-insulator (SOI) is particularly well suited for this because of its relatively low body capacitance, and its wider practical range of body versus well voltage. Developing circuit techniques to leverage this advantage may be critical to the successful commercialization of SOI technology.
Field effect transistors fabricated on a semiconductor substrate contain an inherent parasitic bipolar transistor, as illustrated in FIG. 2. U.S. Pat. No. 5,498,882. Transistor body potential has an influence on threshold voltage, affecting both drive current and leakage current. This is referred to as the body effect. Methods have been proposed in the past to make use of the body effect to modulate the threshold voltage of field effect transistors.
For floating body partially depleted SOI, there is an inherent V
t
modulation which lowers the V
t
when the individual transistor is turned on and raises the V
t
when the transistor is turned off. This modulation is due to the capacitive coupling of the gate to the body of the transistor. However, this effect is hysteretic with floating body SOI, resulting in an unstable threshold voltage.
One approach is to directly connect the gate to the body node, as taught in J-P. Collinge,
IEEE Trans. Electron Devices
, vol. ED-34, no. 4, pp. 845-49, April 1987, and F. Assaderagi et al.,
A Dynamic threshold Voltage MOSFET
(
DTMOS
)
for Ultra
-
Low Voltage Operation
, 1994 IEDM Digest, pp. 809-12, December 1994, both of which are hereby incorporated by reference. This incurs the problem of gate current unless supply voltages are restricted to approximately 0.5 volt or less. Various approaches have been proposed to limit the gate current, but these are cumbersome or restrictive.
In another configuration, the body node is connected to the drain, where the connection is through a transistor gated by the primary transistor input voltage, as taught in U.S. Pat. No. 5,498,882 to T. W. Houston, issued March 1996, and I-Y. Chung et al., 1996 IEEE Int. SOI Conf., pp. 20-21, October 1996, both of which are hereby incorporated by reference. The body-to-drain configuration derives the benefit of dynamic V
t
without gate current and without restriction on operating supply voltage.
Circuit Having Dynamic Threshold Voltage
The present application discloses a modification of the drain-to-body configuration that significantly reduces gate delay and is particularly appropriate for large drivers where a series of inverters is used. The basic configuration is to tie the drain of the transistor to the body of the transistor when the transistor is turned on, and to disconnect it when the transistor is off. Referring particularly to n-channel transistors, when the transistor is off, the drain voltage will generally be high. Thus, if the drain is connected to the body of the transistor when it transitions from off to on, the drain voltage will raise the body voltage, thereby lowering V
t
and increasing the transistor current. The drain to body current will further aid in lowering the drain voltage. As the drain voltage comes down, the body voltage will also be lowered, preparing the transistor for the next on-to-off transition. Advantages of the disclosed methods and structures include the efficient control of the body voltage of a field effect transistor.
REFERENCES:
patent: 5552723 (1996-09-01), Shigehara et al.
patent: 5644266 (1997-07-01), Chen et al.
patent: 5748016 (1998-05-01), Kurosawa
Kuroda, et al., “Variable Supply-Voltage Scheme for Low-Power High-Speed CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 33, No. 3, Mar. 1998.
Brady III W. James
Le Don Phu
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tokar Michael
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