Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-17
2002-12-31
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000, C257S903000
Reexamination Certificate
active
06501138
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as an SRAM, and a method for manufacturing the same.
2. Description of Related Art
A semiconductor memory device has a structure in which peripheral circuits and memory cell arrays consisting of numerous memory cells are formed on a semiconductor substrate. To increase the capacity of a semiconductor memory device, a higher integration of the semiconductor memory device needs to be attained. In particular, an SRAM (Static Random Access Memory) has a large number of device elements that form each memory cell, and therefore a higher integration therefore is required.
The present invention has been made to solve the above-described problems. It is an object of the present invention to provide a semiconductor memory device having a structure that can achieve a higher integration of the semiconductor memory device and a method for manufacturing the semiconductor memory device.
SUMMARY OF PREFERRED EMBODIMENTS
In accordance with an embodiment of the present invention, a semiconductor memory device comprises a semiconductor substrate having a main surface, a well, a plurality of memory cells, a first memory cell region, a second memory cell region, a border region, a well contact region, a first dummy element, a second dummy element, a first transistor and a second transistor. The well is formed in the semiconductor substrate. The first and second memory cell regions are part of the main surface and are located over the well. The memory cells are formed in the first and second memory cell regions. The border region is part of the main surface, and is located over the well on a border between the first memory cell region and the second memory cell region. The well contact region is formed in the well in the border region. The well contact region electrically connects to a wiring layer for fixing the voltage of the well. The first and second dummy elements are formed in the border region and do not function as device elements. The first transistor is a component of the memory cell. The first transistor is formed in the first memory cell region and is located adjacent to the first dummy element. The second transistor is a component of the memory cell. The second transistor is formed in the second memory cell region and is located adjacent to the second dummy element. The border region has a length that is equivalent to the total of one half of the length between one of side sections of a gate electrode of the first transistor on the side of the first dummy element and one of side sections of the first dummy element on the side of the gate electrode of the first transistor, the length of the first dummy element, the length between one of the side sections of the first dummy element on the side of the second dummy element and one of side sections of the second dummy element on the side of the first dummy element, the length of the second dummy element, and one half of the length between one of side sections of a gate electrode of the second transistor on the side of the second dummy element and one of the side sections of the second dummy element on the side of the gate electrode of the second transistor.
In the semiconductor memory device in accordance with the present invention, the border region has a length defined by the above-described values. As a result, while dummy elements are formed, a higher integration of a semiconductor memory device and the reduction of the chip size can be achieved. In other words, a higher integration of a semiconductor memory device can be achieved with the same chip size. On the other hand, the chip size can be reduced with the same number of element devices.
In a preferred embodiment, the border region is located between the first memory cell region and the second memory cell region. A predetermined number of memory cells are formed in each of the first and second memory cell regions. A well contact region is formed in the well in the border region. The well contact region electrically connects to a wiring layer for fixing the voltage of the well containing these memory cells.
Also, dummy elements are formed in the border region. The dummy elements are formed to prevent the optical proximity effect and the loading effect. In other words, if the dummy elements are not formed in the border region, the pattern density in the border region becomes different from the pattern density in the first and second memory cell regions. As a consequence, the optical proximity effect and the loading effect may occur near the border region. Accordingly, a designed memory cell pattern is not obtained near the border region. As a result, memory cells near the border region may become defective.
In a preferred embodiment, the well contact region may be formed in a self-alignment manner, using the first and second dummy elements as masks.
Preferably, the well contact region may be of a first conductivity type. Further, the semiconductor memory device may preferably have word lines wherein the word lines extends from the first memory cell region to the second memory cell region passing through the border region, and the word line are of a second conductivity type.
In accordance with one embodiment of the present invention, each of the memory cells may preferably include a first load transistor, a second load transistor, a first driver transistor and a second driver transistor that form a flip-flop.
The semiconductor memory device in accordance with one embodiment of the present invention may preferably further include a first conductive layer and a second conductive layer. The first and second conductive layers are respectively formed in the first and second memory cell regions. The first conductive layer serves as gate electrodes of the first load transistor and the first driver transistor. The second conductive layer servers as gate electrodes of the second load transistor and the second driver transistor. Preferably, the first conductive layer is generally in the shape of a letter “h” and the second conductive layer is generally in the shape of the number “7”.
In accordance with one embodiment of the present invention, the semiconductor memory device may preferably form an SRAM.
In accordance with one embodiment of the present invention, each of the first and second dummy elements in the semiconductor memory device has a length equivalent to the length of a gate electrode of each of the memory cells.
In accordance with one embodiment of the present invention, one half of the length of each of the first and second dummy elements is greater than an alignment error that occurs when a mask member to be used for forming the well contact region is formed. One half of the length of a dummy element refers to one half of the gate length of the dummy gate when a side wall dielectric film is not formed on a side of the dummy element. When a side wall dielectric film is formed on the side of the dummy element, it refers to one half of the length of the dummy element plus the length of the side wall dielectric film.
In accordance with one embodiment of the present invention, a semiconductor memory device has a semiconductor substrate having a main surface, a well, a plurality of memory cells, a first memory cell region, a second memory cell region, a border region, a first source region, a second source region, a well contact region, a first dummy element and a second dummy element. The well is formed in the semiconductor substrate. The first and second memory cell regions are part of the main surface and are located over the well. The memory cells are formed in the first and second memory cell regions. The border region is part of the main surface, and is located over the well on a border between the first memory cell region and the second memory cell region. The first source region is formed in the well, and extends over the border region and the first memory cell region. The second source region is formed in the well, and extends over the border region and the
Flynn Nathan J.
Hogan & Hartson LLP
Mondt Johannes
Seiko Epson Corporation
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