Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-07-26
2002-10-22
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S225700
Reexamination Certificate
active
06469943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a switching circuit in a semiconductor device, which enables switching from a main circuit to a redundant circuit in the semiconductor device.
2. Background Art
In recent years, ever-greater improvements in density and performance of an IC have been achieved. Moreover, manufacturing processes have also become more minute and precise. Hence, manufacture of a perfectly flawless IC is extremely difficult. For this reason, there has been implemented a method of fabricating a redundant circuit in an IC. If a defective circuit is detected in a test, a flawless redundant circuit will replace it. A replacement is usually implemented with a switching circuit having a fuse.
A switching circuit having a fuse is also used to tune the internal potential of a circuit to an optimal potential for a circuit operation.
FIG. 5
is a schematic diagram showing one example of a prior-art switching circuit.
As illustrated, reference numeral
1
designates a switching element for supplying an address selection signal to a gate terminal of the redundant circuit; and
2
designates a switching element for supplying a pre-charge signal to the gate terminal. A source terminal of the switching element
1
is grounded, and a drain terminal of the switching element
1
is connected to a source terminal of the switching element
2
by way of a fuse
3
. The drain terminal of the switching element
1
is connected further with a power supply Vcc. A word line (WL) selection signal is supplied to a drain terminal of the switching element
4
. The source terminal of the switching element
4
is connected to a redundant (spare) word line (hereinafter abbreviated as “WL”).
Here, reference numeral
5
designates a switching element whose gate terminal is to be supplied with an address selection signal; and
6
designates a switching element whose gate terminal is to be supplied with a pre-charge signal. A source terminal of the switching element
5
is grounded, and a drain terminal of the switching element
5
is connected to a source terminal of the switching element
6
and further to a gate terminal of a switching element
8
by way of an inverter
7
.
A drain terminal of the switching element
6
is connected to a power source Vcc, and a WL selection signal is supplied to a drain terminal of the switching element
8
. A source terminal of the switching element
6
is connected to a main WL. Reference numeral
9
designates a switching element whose gate terminal is connected to a gate terminal of the switching element
4
. A drain terminal of the switching element
9
is connected to a gate terminal of the switching element
8
. Further, a source terminal of the switching element
8
is grounded.
The operation of the switching circuit will now be described.
When an address selection signal is input to the switching elements
1
and
5
, either a main WL for effecting read/write of a main cell or a spare WL for effecting read/write of a spare cell is selected. In an initial state of the redundant circuit, the pre-charge signal is input to the switching elements
2
and
6
, thereby turning on the switching elements
2
and
6
. As a result, nodes N
1
and N
2
enter a high level “H.”
When the redundant circuit is not used, the fuse
3
remains unblown and as is. When an address selection signal is input, the switching elements
1
and
5
are turned on, and a current flows to GND, whereupon the nodes N
1
and N
2
enter a low level “L.” In this state, the switching element
4
is turned off, and the WL selection signal does not enter the spare WL. In this state, the switching element
9
also remains in an OFF state, and hence a node N
3
enters a high level “H.” Further, the switching element
8
is turned on. As a result, the WL selection signal enters a main WL, and a corresponding main cell is selected.
When the redundant circuit is used, the fuse
3
is blown. When an address selection signal is input, the switching elements
1
and
5
are turned on. The node N
2
enters a low level “L,” and the node N
1
remains in a high level “H” as a result of the fuse
3
having been blown. Since the node N
1
is in a high level “H,” the switching element
4
is turned on, and the WL selection signal enters a spare WL, thereby selecting a corresponding spare cell. In contrast, the switching element
9
is turned on as a result of the node N
1
remaining in a high level “H,” and the node N
3
enters a low level “L.” As a result, the switching element
8
is turned off, and the WL selection signal does not enter the main WL. Thus, a corresponding main cell is not selected.
In the prior-art circuit, once the fuse is blown for switching, the circuit cannot be restored to its original state. Therefore, if a redundant circuit is found to be defective after the fuse is blown, a semiconductor device including the redundant circuit must be taken as defective.
SUMMARY OF THE INVENTION
The purpose of the present invention is to provide a new switching circuit between a main circuit and a redundant circuit in a semiconductor device, which enable to nullify switching after blowing a fuse.
According to one aspect of the present invention, a switching circuit comprises one-way-switching means, for example a fuse, to switch from the main circuit to the redundant circuit. And the switching circuit also comprises nullifying means to nullify switching by the one-way-switching means.
The nullifying means may comprise a switching element, such as a transistor switch, connected in parallel with the one-way-switching means, and a control means to control the switching element. The control means may operate to tentatively turn on the switching element in a test mode to enable to ascertain whether a nullification of switching by the one-way-switching element is effective or not. The control means preferably has a fuse to be blown to fix the switching element ON, that is, to fix the nullification.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
REFERENCES:
patent: 5058059 (1991-10-01), Matsuo et al.
patent: 5258953 (1993-11-01), Tsujimoto
patent: 5337277 (1994-08-01), Jang
patent: 5657280 (1997-08-01), Shin et al.
patent: 5699306 (1997-12-01), Lee et al.
patent: 6094386 (2000-07-01), Kohyama
patent: 6118710 (2000-09-01), Tsuji
patent: 6144592 (2000-11-01), Kanda
patent: 6188618 (2001-02-01), Takase
patent: 62-235750 (1987-10-01), None
patent: 6-216253 (1994-08-01), None
patent: 9-213097 (1997-08-01), None
patent: 10-335594 (1998-12-01), None
Le Thong
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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