Silicon carbide CMOS devices

Details Silicon carbide CMOS devices Silicon carbide CMOS devices

1996-04-15

2002-02-05

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Specified wide band gap semiconductor material other than...

Diamond or silicon carbide

C257S351000, C257S369000, C257S383000, C257S769000, C438S931000

Reexamination Certificate

active

06344663

ABSTRACT:

This invention was made with Government support and the Government has certain rights in this invention.
FIELD OF THE INVENTION
The present invention relates to metal/polysilicon-oxide semiconductor (MOS) devices formed in silicon carbide. More particularly the present invention related to complementary metal/polysilicon-oxide-semiconductor devices commonly known as CMOS formed in silicon carbide.
BACKGROUND OF THE INVENTION
Complimentary MOS (CMOS) integrated devices are monolithically integrated p-channel and n-channel transistors which are optionally interconnected in a single device. CMOS devices provide the basis for many integrated circuits such as operational amplifiers, sensing devices, digital logic, memory devices, and microprocessors. CMOS technology is readily adaptable to mixed analog and digital applications. The availability of active or current source loads makes it possible to generate large voltage gains with relatively small supply voltages and currents. CMOS also provides for low power digital circuits. CMOS is also attractive as a technology because lower power supply voltage operation and reduced circuit design complexity enhances reliability over all operating conditions.
To produce a CMOS device, a single substrate or die must be capable of producing transistors of complementary type. Thus, a single die must support both p-type and n-type regions to provide for the p-type and n-type channels of the complementary devices. Previous CMOS devices have been fabricated in silicon but have not been produced using silicon carbide. The difficulty in fabricating regions of opposite conductivity silicon carbide suitable for producing complementary transistors on a single die or wafer, in addition to the general difficulty in producing a p-channel silicon carbide MOS field effect transistor have prevented production of CMOS in silicon carbide.
Because of the advantages that CMOS integrated devices have over devices comprised solely of p-channel or n-channel transistors, it is desirable to overcome the barriers in silicon carbide to allow for the development of a CMOS silicon carbide integrated device technology.
OBJECT AND SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a method of fabrication of a monolithic silicon carbide integrated device with a p-channel transistor and an n-channel transistor on the same die or wafer. It is a further object of the present invention to provide a CMOS device formed in silicon carbide.
The methods and structures of the present invention provide an integrated device formed of silicon carbide. The integrated device has a first silicon carbide MOS field effect transistor formed in silicon carbide. This first MOS device has a channel region formed in p-type conductivity silicon carbide. Also in the integrated device is provided a second silicon carbide MOS field effect transistor formed in silicon carbide. This second MOS device has a channel region formed in n-type conductivity silicon carbide. Optionally, the drain of the first silicon carbide MOS field effect transistor is electrically connected to the drain of the second silicon carbide MOS field effect transistor.
In a preferred embodiment of the present invention the drain and source contacts of the first and second MOS field effect transistors are formed of the same material. The preferred material for these contacts is nickel.
Preferred structures provided by the present invention include structures for a complementary MOS integrated device which includes a layer of a first conductivity type silicon carbide which may be a substrate or an epitaxial layer. A well region of a second conductivity type silicon carbide is formed in the silicon carbide layer. A plurality of regions of the second conductivity type silicon carbide are formed in the silicon carbide layer to form a layer source region and a layer drain region in the silicon carbide layer. A plurality of regions of the first conductivity type silicon carbide are formed in the well region to form a well source region and a well drain region in the well region. A gate dielectric layer is formed between the layer source and the layer drain regions and extending over at least a portion of the layer drain and layer source regions. Likewise a gate dielectric layer is formed between the well source and the well drain regions and extending over at least a portion of the well source and well drain regions. A layer gate electrode is formed on the gate dielectric layer formed between the layer source region and the layer drain region so as to provide an active channel region in the first conductivity type silicon carbide layer between the layer source and the layer drain when a bias is applied to the layer gate electrode. A well gate electrode is also formed on the gate dielectric layer formed between the well source region and the well drain region so as to provide an active channel region in the second conductivity type well region between the well source and the well drain when a bias is applied to the well gate electrode.
A well source contact may also be formed on the well source region and a well drain contact may be formed on the well drain region. Similarly a layer source contact may be formed on the layer source region and a layer drain contact formed on the layer drain region.
In an alternate embodiment of the present invention, a plurality of well channel stop regions are formed in the well region. The stop regions are formed of the second conductivity type silicon carbide and have a higher carrier concentration than the well region. The channel stops are positioned such that the well source region and the well drain region are displaced between the channel stop regions. A plurality of layer stop regions may also be formed in the silicon carbide layer adjacent the layer source and the layer drain regions. The layer stop regions are formed of the first conductivity type silicon carbide and have a higher carrier concentration than the silicon carbide layer. The layer stop regions are formed such that the layer source and the layer drain regions are displaced between the layer stop regions.
In addition to the formation of the basic transistor devices, embodiments of the present invention may include an isolation layer formed on the silicon carbide layer, the well region, the well source, gate and drain contacts and the layer source, gate and drain contacts. This isolation layer allows for interconnections of the various silicon carbide devices. This interconnection may be achieved by a plurality of metallization regions for selectively providing connection to the well source, gate and drain contacts and the layer source, gate and drain contacts through connection windows formed in the isolation layer.
In a further embodiment of the present invention, a protective layer is formed on the exposed surfaces of the integrated device to protect the device from environmental damage. Connection pads may be formed in a connection pad window through the protective layer to allow for connection to any underlying region such as the interconnecting metallization.
In a further alternate embodiment of the present invention, at least one of the MOS devices has a source and drain layer region that is self-aligned to the gate electrode.
The method embodiments of the present invention include a method of forming a complementary MOS integrated device in silicon carbide. The method includes the steps of forming a first silicon carbide MOS field effect transistor in silicon carbide and having a channel region formed in p-type conductivity silicon carbide and forming a second silicon carbide MOS field effect transistor in silicon carbide which has a channel region formed in n-type conductivity silicon carbide.
In a particular embodiment of the methods of the present invention, the method of forming a silicon carbide integrated device includes the steps of forming a lightly doped silicon carbide layer of a first conductivity type having highly doped source and drain regions of a second conductivit

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