Semiconductor device comprising MIS field-effect transistor,...

Details Semiconductor device comprising MIS field-effect transistor,... Semiconductor device comprising MIS field-effect transistor,...

1998-06-15

2002-02-05

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S344000

Reexamination Certificate

active

06344677

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device comprising a MIS field-effect transistor and a semiconductor device comprising a MIS field-effect transistor that is fabricated by that method.
2. Description of Related Art
Various methods of fabricating a metal-insulator semiconductor (MIS) field-effect transistor have been disclosed, such as that in Japanese Patent Application Laid-Open No. 9-162402, for example. The method of fabricating an MIS field-effect transistor disclosed in that document will be descried below.
A p-type well
202
is formed on the main surface of a p-type silicon substrate
200
, as shown in
FIG. 40. A
field oxide layer
204
is formed around the p-type well
202
, to separate the elements. A gate oxide layer
206
is formed on the p-type well
202
. A polysilicon layer
208
is formed on the gate oxide layer
206
.
The polysilicon layer
208
is etched selectively to form a gate electrode
212
, as shown in FIG.
41
. The gate electrode
212
and the field oxide layer
204
are used as a mask for the implantation of ions of arsenic into the main surface of the silicon substrate
200
, to form n
−
-type regions
214
. A chemical vapor deposition (CVD) method is then used to form a silicon nitride layer
210
on the main surface of the silicon substrate
200
in such a manner as to cover the gate electrode
212
. Anisotropic etching is used to etch back this silicon nitride layer
210
so that the remaining silicon nitride layer
210
has a thickness of 10 nm and shields the side surfaces of the gate electrode
212
and the side surfaces of the gate oxide layer
206
. The formation of the silicon nitride layer
210
at positions shielding the side surfaces of the gate oxide layer
206
ensures that the supply of oxygen to the gate oxide layer
206
is prevented. This prevents the occurrence of “bird's beak” in the gate oxide layer
206
of the gate. Gate bird's beak is a cause of deterioration of the characteristics of the MIS field-effect transistor. The thickness of the silicon nitride layer
210
is set to 10 nm for reasons given below. A source/drain of the resultant MIS field-effect transistor consists of three regions: an n
−
-type region, an n-type region, and an n+-type region. The n
−
-type region is positioned below the silicon nitride layer
210
. If the thickness of the silicon nitride layer
210
is less than 10 nm, the width of the n
−
-type region is also less than 10 nm. If the width of the n
−
-type region is less than 10 nm, the n-type region becomes absorbed into the neighboring n-type region and it can no longer function as an n
−
-type region.
The gate electrode
212
, the silicon nitride layer
210
, and the field oxide layer
204
are used as a mask for the implantation of arsenic ions into the main surface of the silicon substrate
200
, to form n-type regions
218
as shown in
FIG. 42. A
silicon oxide layer is then formed on the main surface of the silicon substrate
200
by a CVD method, to cover the gate electrode
212
. This silicon oxide layer is etched back by using anisotropic etching to form a side-wall silicon oxide layer
216
in such a manner that it shields the silicon nitride layer
210
.
The gate electrode
212
, the silicon nitride layer
210
, the side-wall silicon oxide layer
216
, and the field oxide layer
204
are used as a mask for the implantation of arsenic ions into the main surface of the silicon substrate
200
, to form n
+
-type regions
220
as shown in FIG.
43
.
An intermediary insulation layer
222
is formed over the entire surface of the silicon substrate
200
so as to cover the gate electrode
212
, as shown in FIG.
44
. Contact holes
224
are formed in the intermediary insulation layer
222
to reach the n
+
-type regions
220
. A conductive layer is formed on top of the intermediary insulation layer
222
and within the contact holes
224
. A wiring layer
226
is formed by subjecting this conductive layer to given patterning. The MIS field-effect transistor is fabricated by the above steps.
Referring back to
FIG. 41
, the n
−
-type regions
214
are formed by the implantation of ions into the main surface of the silicon substrate
200
, using the gate electrode
212
as a mask. The side surfaces of the gate oxide layer
206
are exposed during this ion implantation. Since the side surfaces of the gate oxide layer
206
are exposed, ions strike the side surfaces of the gate oxide layer
206
. This results in places at edge portions of the gate oxide layer
206
where the bonding of the crystalline structure of the gate oxide layer are broken. There are three main problems caused by breakage of the bonding of the crystalline structure in the gate oxide layer: the dielectric breakdown voltage drops at the places in the gate insulation layer where the crystalline structure is damaged, so the dielectric breakdown voltage of the entire gate insulation layer drops; carriers flow through the places in the gate insulation layer where the crystalline structure is damaged, causing a leakage current through the gate insulation layer; and carriers flowing through the channel can easily be trapped at the places in the gate insulation layer where the crystalline structure is damaged. These all change the characteristics of the MIS field-effect transistor. The long-term reliability of the MIS field-effect transistor also falls.
If tilted ion implantation
258
in particular is used to form a source/drain
254
, as shown in
FIG. 45
, a large number of ions will strike the side surfaces of the gate oxide layer
206
directly. This makes it more likely for large numbers of places where the bonding of the crystalline structure are broken to appear in the edge portions of the gate oxide layer
206
. The reasons for using tilted ion implantation will now be discussed. If this tilted ion implantation
258
is used to create the source/drain
254
, edge portions
256
of the source/drain
254
are formed at positions overlapping the gate electrode
212
. This will prevent carriers that are flowing through the channel from jumping into the gate oxide layer
206
. In other words, if a side surface of one of the n
−
-type regions
214
of the source or drain is positioned directly below a side surface of the gate electrode
212
, concentrations in electrical field will occur at the places indicated by arrows A. These electrical field concentrations make it easy for the carriers flowing in the channel to jump into the gate oxide layer
206
. If carriers jump into the gate oxide layer
206
, the characteristics of the gate oxide layer
206
will deteriorate.
Note that the n
−
-type regions
214
shown in
FIG. 41
could also be formed by diffusion. The side surfaces of the gate oxide layer
206
will still be exposed, even when the n
−
-type regions
214
are formed by diffusion. This means that the diffused impurity will go through the side surfaces of the gate oxide layer
206
into the crystalline structure of the gate oxide layer
206
. This will cause the dielectric breakdown voltage of the gate oxide layer
206
to drop.
With the fabrication of a MIS field-effect transistor, a silicide layer is often formed on the upper surface of the gate electrode, to lower the electrical resistance of the gate electrode. This is discussed below.
A p-type well
232
is formed in a main surface of a p-type silicon substrate
230
, as shown in
FIG. 46. A
field oxide layer
234
is formed around the p-type well
232
. A gate oxide layer
236
and a polysilicon layer are then formed on the main surface of the silicon substrate
230
. A gate electrode
238
is then formed by subjecting the polysilicon layer to given patterning. The gate electrode
238
and the field oxide layer
234
are used as a mask for the implantations of ions into the main surface of the silicon substrate
230
, to form n
−
-type regions
242
. A silicon oxide layer is then fo

Affiliated with

Also associated with

Rating

Semiconductor device comprising MIS field-effect transistor,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device comprising MIS field-effect transistor,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device comprising MIS field-effect transistor,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2935705