Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate
2000-03-27
2002-10-15
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
On insulating carrier other than a printed circuit board
C257S676000
Reexamination Certificate
active
06465877
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor packaging. More particularly, this invention relates to a chip scale semiconductor package that includes a flex circuit bonded to a semiconductor die, and interconnects electrically connecting contacts on the die to external contacts on the flex circuit.
BACKGROUND OF THE INVENTION
One type of semiconductor package is referred to as a “chip scale package”. Chip scale packages are also referred to as “chip size packages”, and the dice are referred to as being “minimally packaged”. Chip scale packages can be fabricated in “uncased” or “cased” configurations. Uncased chip scale packages have a “footprint” (peripheral outline) that is about the same as an unpackaged die. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die. For example, a footprint for a typical cased chip scale package can be about 1.2 times the size of the die contained within the package.
Typically, a chip scale package includes a substrate bonded to the face of the die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. The substrate for a chip scale package can comprise a flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, glass or FR-4. The external contacts for one type of chip scale package include solder balls arranged in a dense array, such as a ball grid array (BGA), or a fine ball grid array (FBGA). These dense arrays permit a high input/output capability for the chip scale package. For example, a FBGA on a chip scale package can include several hundred solder balls.
One aspect of chip scale packages is that the dense arrays of external contacts are difficult to fabricate. In particular, reliable electrical interconnections must be made between the external contacts for the package, and contacts on the die contained within the package. Typically, the contacts on the die are thin film aluminum bond pads in electrical communication with integrated circuits on the die.
FIG. 1
illustrates a prior art chip scale package
10
. The package
10
includes: a semiconductor die
12
; a polymer tape
14
bonded to a face of the die
12
; and an encapsulant
16
bonded to the face and sides of the die
12
. In addition, the package
10
includes an adhesive layer
18
for bonding the polymer tape
14
to the die
12
, and a dense array of solder balls
20
formed on the polymer tape
14
. Metal beams
22
are bonded to the solder balls
20
, and to device bond pads
24
on the die
12
. The metal beams
22
are also encapsulated in the encapsulant
16
.
A representative process flow for forming the chip scale package
10
includes bonding one or more dice
10
to a strip of the polymer tape
14
. The metal beams
22
can then be bonded to the device bond pads
24
. Next, the encapsulant
16
can be formed, and the solder balls
20
attached to the metal beams
22
. The individual packages
10
can then be singulated from the strip of polymer tape
14
and tested.
Typically, a thermosonic bonding process using gold or gold plated materials are employed to bond the metal beams
22
. In addition, specialized bonding tools are required to make the bonds between the metal beams
22
and the bond pads
24
. The metal beams
22
are also subjected to stresses from the bonding and encapsulation processes, and during subsequent use of the package
10
. These stresses can cause the bonds to weaken or pull apart.
The present invention is directed to an improved chip scale semiconductor package including dense array external contacts, and improved interconnects between the external contacts and contacts on the die.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved chip scale package, and a method for fabricating the package are provided. The package comprises a singulated semiconductor die, and a flex circuit bonded to a face of the die in electrical communication with die contacts (e.g., device bond pads). The flex circuit includes a polymer substrate on which external contacts, such as an array of solder bumps (e.g., BGA, FBGA), are formed. The flex circuit also includes conductors on the polymer substrate, in electrical communication with the external contacts.
In addition to the die and flex circuit, the package includes interconnects electrically connecting the die contacts to the flex circuit conductors. A wafer level fabrication process can be used to bond the flex circuit and form the interconnects. Singulation of the wafer forms the individual packages.
In a first embodiment, the interconnects comprise solder bumps on the die contacts, and a conductive polymer layer which forms separate electrical paths between the solder bumps and the flex circuit conductors. Suitable materials for forming the conductive polymer layer include z-axis anisotropic adhesives, and z-axis epoxies applied as a viscous paste, and then cured under compression.
In a second embodiment, the interconnects comprise conductive polymer bumps on the die contacts, which are bonded to the flex circuit conductors. Suitable materials for forming the polymer bumps include isotropic adhesives that are conductive in any direction (e.g., silver filled silicone), and anisotropic adhesives that are conductive in only one direction (z-axis epoxies). In addition, an electrically insulating adhesive layer, such as silicone, can be used to bond the flex circuit to the die, and to absorb thermal stresses. Furthermore, the polymer bumps can be applied to the die contacts in a semi-cured, or B-stage condition, and then fully cured while in physical contact with the die contacts. For semi-cured polymer bumps, a compliant elastomeric base material can include dendritic metal particles for penetrating oxide layers on the die contacts, and a solvent to permit partial curing at room temperature.
In a third embodiment, the interconnects comprise solder bumps on the die contacts, bonded to solder bumps on the flex circuit conductors. A compliant layer can also be formed between the die and flex circuit to absorb thermal stresses. Bonding of the solder bumps can be with thermocompression bonding, thermosonic bonding, or ultrasonic bonding.
In a fourth embodiment, the interconnects comprise solder bumps on the flex circuit conductors, and polymer bumps on the die contacts.
In a fifth embodiment, the interconnects comprise solder bumps on the die contacts, bonded to plated metal bumps on the flex circuit conductors. A compliant layer can also be formed between the flex circuit and die, as an adhesive and thermal expansion joint. Suitable materials for the plated metal bumps include gold, palladium and gold plated metals.
In a sixth embodiment, the interconnects comprise rivet-like, bonded connections between the die contacts and the flex circuit conductors. The bonded connections include a first set of metal bumps on the die contacts, and a second set of metal bumps formed through openings in the conductors and bonded to the first set of metal bumps. Both sets of metal bumps can be formed using a bonding tool of a wire bonding apparatus. Alternately, the metal bumps can be formed using a solder ball bumper apparatus configured to place and reflow a first set of pre-formed solder balls on the die contacts, and then to place and reflow a second set of pre-formed solder balls through the openings in the flex circuit conductors onto the first set.
In a seventh embodiment, the interconnects comprise bonded connections between the flex circuit conductors and the die contacts formed using thermocompression bonding, thermosonic bonding, or a laser pulse. In this embodiment the polymer substrate can include openings which provide access for a bonding tool to portions of the flex circuit conductors. Using the openings the tool presses and bonds the portions to the die contacts. In addition, adhesive dots can be formed between the flex circuit substrate, and the die to align and attach the flex circuit to the die. The die contacts can also i
Brooks Mike
Farnworth Warren M.
Wood Alan G.
Gratton Stephen A.
Potter Roy
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