Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2000-02-15

2002-12-31

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000

Reexamination Certificate

active

06501125

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device and its manufacturing method and, particularly, to a nonvolatile semiconductor storage device and its manufacturing method.
2. Description of Related Art
FIGS. 17-30
show a process for forming a memory cell portion of a conventional semiconductor device, particularly a nonvolatile semiconductor storage device.
As shown in
FIGS. 17 and 18
, device isolation regions
102
are formed on the main surface of a p-type silicon substrate
101
.
As shown in
FIG. 19
, after the main surface of the p-type silicon substrate
101
is cleaned, a tunnel oxide film
103
of about 100 Å in thickness is formed by thermal oxidation in areas other than above the device isolation regions
102
. A phosphorus-doped polysilicon film
104
a
of about 1,000 Å in thickness is formed on the surface of the tunnel oxide film
103
by low-pressure CVD, and then a silicon nitride film
105
a
of about 1,000 Å in thickness is deposited on the phosphorus-doped polysilicon film
104
a.
Then, as shown in
FIG. 20
, after a resist (not shown) is formed in a desired pattern on the silicon nitride film
105
a
by photolithography, first-layer floating gates
104
b
are formed by etching the phosphorus-doped polysilicon film
104
a
and the silicon nitride film
105
a
by using the resist as a mask. Silicon nitride films
105
b
are formed on the respective first-layer floating gates
104
b.
After the resist is removed, n
−
regions (diffusion regions)
106
are formed by implanting phosphorus ions at energy of 50 eV at a dose of 2×10
13
cm
−2
.
Then, as shown in
FIG. 21
, a thick silicon oxide film
107
of about 2,000 Å in thickness is deposited by low-pressure CVD.
Then, as shown in
FIG. 22
, sidewalls
108
of silicon oxide films are formed on the first-layer floating gates
104
b
by anisotropic etching. Then, annealing is performed at about 900° C. in a nitrogen atmosphere. Then, n
+
regions (diffusion regions)
109
are formed under the tunnel insulating film
103
by implanting arsenic ions at energy of 50 eV at a dose of 5×10
15
cm
−2
.
Then, as shown in
FIG. 23
, a thick silicon oxide film
110
of about 4000 Å in thickness is deposited by CVD.
Then, as shown in
FIG. 24
, the silicon nitride films
105
b
on the respective first-layer floating gates
104
b
are exposed by etching back the silicon oxide film
110
by dry etching.
Then, as shown in
FIG. 25
, the silicon nitride films
105
b
on the respective first-layer floating gates
104
b
are removed by using a heated phosphoric acid.
Then, as shown in
FIG. 26
, the silicon oxide film
110
and the sidewalls
108
are etched back by dry etching.
Then, as shown in
FIG. 27
, a phosphorus-doped polysilicon film
111
a
of about 1,000 Å in thickness is deposited on the etched-back silicon oxide film
110
and sidewalls
108
by low-pressure CVD. Then, a resist
112
is formed in a desired pattern on the phosphorus-doped polysilicon film
111
a
by photolithography.
Then, as shown in
FIG. 28
, second-layer floating gates
111
b
are formed by etching the phosphorus-doped polysilicon film
111
a
by using the resist
112
as a mask.
Subsequently, as shown in
FIG. 29
, a silicon oxide film
113
of about 200 Å in thickness is deposited on the second-layer floating gates
111
b
and the silicon oxide film
110
by low-pressure CVD.
As shown in
FIG. 30
, a phosphorus-doped polysilicon film
114
is deposited on the silicon oxide film
113
and then a silicon oxide film
115
is formed on the phosphorus-doped polysilicon film
114
. After a resist is patterned by photolithography, the silicon oxide film
115
and the phosphorus-doped polysilicon film
114
are patterned. The resist is then removed. Then, after a resist is formed in a peripheral circuit portion by photolithography, floating gate electrodes
111
c
of memory transistors are formed from the phosphorus-doped polysilicon films
111
b
and etched first-layer floating gates
104
c
are formed by etching the silicon insulating film
113
, the phosphorus-doped polysilicon film
111
b,
and the first-layer floating gates
104
b
by using the silicon oxide film
115
in the memory cell portion as a mask.
Subsequently, n-channel transistors and p-channel transistors are formed in the peripheral circuit portion.
Then, a boron-phosphorus glass layer
121
of about 10,000 Å is deposited on the silicon oxide film
115
by CVD. After the boron-phosphorus glass layer
121
is burnt and tightened by performing a heat treatment at about 850° C. for about 30 minutes in a nitrogen atmosphere, a resist (not shown) is formed in a desired pattern on the boron-phosphorus glass layer
121
by photolithography. After contact holes are formed by etching the boron-phosphorus glass layer
121
using the resist as a mask, an aluminum-silicon-copper (Al—Si—Cu) alloy film
122
is deposited by sputtering. Then, after a resist (not shown) is formed in a desired pattern by photolithography, an Al—Si—Cu wiring
122
is formed by etching the Al—Si—Cu alloy film
122
by using the resist as a mask.
In the above conventional nonvolatile semiconductor device, information (data) is stored in the memory cell transistors depending on whether electrons are injected in or released from the first-layer floating gates
104
c
and the second-layer floating gates
111
c.
In a state that electrons are injected in the first-layer floating gate
104
c
and the second-layer floating gate
111
c,
the threshold voltage of a memory cell transistor has a large value Vthp. This state is called a programmed state. In this case, data “0” is stored in the memory cell transistor. Since electrons accumulated in the first-layer floating gate
104
c
and the second-layer floating gate
111
c
do not disappear semi-permanently as long as they are left as they are, the stored data is also held semi-permanently.
In a state that electrons are released from the first-layer floating gate
104
c
and the second-layer floating gate
111
c,
the threshold voltage of a memory cell, transistor has a small value Vthe. This state is called an erased state. In this case, data “1” is stored in the memory cell transistor. Data “0” or “1” that is stored in a memory cell transistor can be read out by detecting one of the programmed state and the erased state. Certain stored data may be defined as either “0” or “1”; it is also possible to make a definition that data “1” is stored in the programmed state and data “0” is stored in the erased state.
In the programmed state, a high voltage Vpp (usually about 20 V) is applied to the control gate
114
and the n-type diffusion layer
109
a
and the silicon substrate
101
are grounded. Because of the grounding, electrons are generated in the channel that is formed between the n-type diffusion layers
109
a
and
109
b.
The electrons generated in the channel tunnel through the energy barrier of the tunnel insulating film
103
and are injected into the first-layer floating gate
104
c and the second-layer floating gate
111
c.
As a result, the threshold voltage of the memory cell transistor increases to the large value Vthp.
At the time of erasing, a high voltage −Vpp (usually about −20 V) is applied to the control gate
114
and the n-type diffusion layer
109
a
and the silicon substrate
101
are grounded. Because of the grounding, electrons are released from the first-layer floating gate
104
c
and the second-layer floating gate
111
c
to the silicon substrate
101
by the tunneling phenomenon. As a result, the threshold voltage of the memory cell transistor decreases to the small value Vthe.
Each memory cell of the above conventional nonvolatile semiconductor storage device consists of a capacitor C
1
that is composed of the control gate
114
, the silicon oxide film
113
, the second-layer floating gate
111
c,
and the first-layer floating gate
104
c
and a capacitor C
2
that is composed of th

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