Method for fabricating a dual damascene structure

Details Method for fabricating a dual damascene structure Method for fabricating a dual damascene structure

2001-02-22

2002-06-11

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S633000, C438S637000

Reexamination Certificate

active

06403470

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90100097, filed Jan. 3, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a fabrication method for multilevel interconnects. More particularly, the present invention relates to a fabrication method for a dual damascene structure.
2. Description of Related Art
The conventional fabrication method for the multilevel interconnects includes depositing a metal layer on an insulation layer, for example, a silicon oxide layer, which is used to isolate the metal layer. Subsequent to the formation of the metal layer, the metal layer is defined with the pre-defined conductive line pattern. An opening vertical to the conductive line layers is formed between the conductive line layers. A metal layer, which can be the same material or a different material from the conductive layer, is formed to fill the opening to complete the vertical connection of the conductive layer. As the number of the conductive line layers increases in integrated circuits, the metal layer design with two or more layers has gradually become a requirement for many integrated circuits. Inter-metal dielectrics (IMD) are often used to isolate metal layers. The conductive line that is used to connect the upper and the lower metal layers is known as a via in the semiconductor industry.
The dual damascene technique is a technique of concurrently forming the via the interconnects. The technique includes first forming an insulation layer on the substrate. After being planarized, the insulation layer is etched according the required metal conductive line pattern and the position of the via to form a via opening and a trench. Thereafter, a metal layer is deposited on the substrate, filling the via opening and the trench to concurrently form the metal conductive line and the via. Subsequently, chemical-mechanical polishing (CMP) is conducted to planarize the surface of the device to complete the fabrication of a dual damascene structure.
According to the conventional approach in forming the dual damascene structure, the etching technique and the etching stop layer are used to form sequentially the via opening and the trench. The profiles and the depths of the via opening and the trench are thus difficult to control. Moreover, since an etching stop layer is used, it is also difficult to effectively lower the dielectric constant of the inter-metal dielectrics.
SUMMARY OF THE INVENTION
The present invention provides a fabrication method for a dual damascene structure. This method uses hot filament chemical vapor deposition method to form a dielectric layer above the via opening without filling the via opening. Thus, in the subsequent formation of the trench, it only needs to form the opening in the dielectric layer. Moreover, not only the application of an etching stop layer is precluded, the dielectric constant of the inter-metal dielectrics is also effectively reduced. The difficulties of controlling the depths and the profiles of the via opening and the trench is resolved. The technique of hot filament chemical vapor deposition can refer to Karen K. Gleason, “Controlling the Molecular Architecture of Fluorocarbon CVD Dielectric Thin Films”, Symposium of “Concepts and Needs for Low Dielectric Constant<0.15 micron Interconnect Materials: Now and Next Millennium” November, 1999, p. 310-336.
The present invention provides a fabrication method for a dual damascene structure. The method includes forming a first dielectric layer on a substrate, wherein a first conductive layer is already formed therein. The first dielectric layer is then patterned to form a via opening, exposing the first conductive layer. Thereafter, a second dielectric layer is formed on the first dielectric layer by hot filament chemical vapor deposition, wherein the second dielectric layer does not fill the via opening. The second dielectric layer is then patterned to form a trench, wherein the trench and the via opening together form a dual damascene opening. After this, a second conductive layer fills the dual damascene opening to complete the manufacturing of the dual damascene structure.
The present invention uses the hot filament chemical vapor deposition to form the second dielectric layer, which does not fill the via opening. The profile of the via opening is thus remained unchanged. Furthermore, in the subsequent formation of the trench, it only needs to form an opening in the second dielectric layer. The problems of controlling the profiles of the via opening and the trench after etching in forming the dual damascene structure are thus resolved.
The present invention employs the hot filament chemical vapor deposition to form the second dielectric layer without filling the via opening. Therefore, in the subsequent formation of the trench, it only needs to form the opening in the second dielectric layer. The application of an etching stop layer is thus precluded and the dielectric constant of the dielectric layer is thereby effectively reduced.
The present invention employs the hot filament chemical vapor deposition to form the second dielectric layer, which is porous. Furthermore, the porosity ratio can be adjusted accordingly. As a result, the dielectric constant of the dielectric layer can be effectively reduced to increase the isolation effect.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6066557 (2000-05-01), Lukanc et al.
patent: 2001-298083 (2001-10-01), None
“Controlling the Molecular Architecture of Fluorocarbon CVD Dielectric Thin Films” Karen K. Gleason/pp. 310-335. Department of Chemical Engineering. MIT (date unknown).

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