Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-08-31
2002-08-20
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S622000, C438S623000, C438S624000, C438S637000, C438S652000, C438S653000, C438S783000
Reexamination Certificate
active
06436850
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing high-density, multi-metal layer semiconductor devices exhibiting reliable interconnection patterns. The invention has particular applicability in manufacturing high-density, multi-metal layer semiconductor devices with design features of 0.25 micron and under.
BACKGROUND OF THE INVENTION
The escalating requirements for high densification and performance associated with ultra-large scale integration semiconductor devices necessitate design features of 0.25 micron and under, such as 0.18 micron, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 micron and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal forming technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon (Si), with conductive contacts formed therein for electrical connection with an active region in or on the substrate, such as a source/drain region. A metal layer, such as of aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask having a pattern corresponding to a desired conductive pattern is formed on the metal layer. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is then planarized, for example, by conventional etching or chemical-mechanical polishing (CMP) techniques.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 micron and below, such as 0.18 micron and below, it becomes increasingly difficult to satisfactorily fill in the interwining spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable inter-level interconnection structure. A through-hole is typically formed in a dielectric layer to expose a selected portion of an underlying metal feature, wherein the exposed portion of the metal feature at the bottom of the through-hole serves as a contact pad. Upon filling the through-hole with conductive material, such as a metal plug, to form a conductive via, the bottom surface of the conductive via is in contact with the underlying metal feature.
Because many large scale integration (LSI) devices presently manufactured are very complex and require multiple levels of metallization for interconnections, it has been common to repeat the above-described via formation process multiple times, e.g., to form as many as five levels of metallization interconnected by conductive vias. A semiconductor device of the above-described type including, for illustrative purposes, three levels of metallization, and a manufacturing process therefor is explained in more detail below with reference to FIG.
1
.
As schematically shown in
FIG. 1
, a semiconductor device
1
of the above-described type comprises a semiconductor substrate
8
, typically a doped monocrystalline silicon wafer, having formed therein or thereon at least one active region (not shown for illustrative simplicity), e.g. a source/drain region, a transistor, a diode, and/or other semiconductor elements well known in the art. A first dielectric layer
9
of e.g. a silicon oxide, is formed over substrate
8
and includes at least one electrical contact
10
, schematically shown for illustration, for electrically connecting the active structure(s) of semiconductor substrate
8
to a first metal feature
11
comprising a first patterned metal layer formed over first dielectric layer
9
. First metal feature
11
is typically formed as a composite structure comprising a thin lower metal layer
11
A, of e.g., titanium (Ti) or tungsten (W), a thicker intermediate or primary conductive layer
11
B, of e.g., aluminum (Al) or an Al alloy, and an upper, thin, electrically conductive antireflective coating (ARC)
11
C, of e.g., titanium nitride (TiN). After formation of the first metal feature
11
, a second dielectric layer
12
, referred to as a “gap-fill” layer, is deposited to fill the interwiring spaces
12
A, i.e., the spaces between the first metal features
11
. Materials employed for the gap-filling second dielectric layer
12
include, for example, spin-on glass (SOG), high density plasma oxide (HDPO), and low dielectric constant (“low k”) materials having an as-deposited dielectric constant below 3.9, such as polytetrafluoroethylene (TEFLON™), parylene, polyimide, hydrogen silsesquioxane (HSQ), and benzocyclobutene (BCB), the latter two materials being preferred.
A third dielectric layer
13
, typically a silicon oxide obtained by plasma enhanced chemical vapor deposition (PECVD) of silane (SiH
4
) in an N
2
O atmosphere or by PECVD of tetraethylorthosilicate (TEOS) in the presence of oxygen, is then formed over the second dielectric layer
12
and planarized. A thorough-hole
14
, extending through the second and third dielectric layers
12
and
13
, is then formed in accordance with conventional practices so that an upper surface portion
11
D of the first metal feature
11
is exposed by and encloses the bottom opening of the through-hole
14
, thereby providing a contact pad for a metal plug
15
, typically of tungsten (W), forming a via
16
. Layer
17
shown as lining the internal surfaces of the through-hole
14
, is formed prior to metal plug
15
filling and serves as an adhesion promoting and/or barrier layer. Layer
17
is typically formed of an electrically conductive refractory material such as TiN, Ti—W, and Ti—TiN.
Second metal feature
18
comprising a metal composite similar to first metal feature
11
is then formed by depositing a composite metal layer atop the third dielectric layer
13
and in electrical contact with the first metal feature
11
through via
16
, and patterning the layer by means of conventional techniques. Conductive via
16
thus electrically connects first metal feature
11
with second metal feature
18
. As illustrated, second metal feature
18
comprises a thin, lower metal layer
18
A, thicker intermediate or primary layer
18
B, and thin, upper, electrically conductive AR layer
18
C.
After formation of the second metal feature
18
, a fourth dielectric layer
19
of low k gap-fill material similar to that of second dielectric layer
12
is formed so as to fill the interwiring spaces
19
A between the second metal features
18
. Fifth dielectric layer
20
of a material similar to that of third dielectric layer
13
is then formed over fourth dielectric layer
19
and planarized by such techniques as employed previously with third dielectric layer
13
. As before, a through-hole
21
is formed to extend through fourth and fifth dielectric layers
19
,
20
so as to expose a portion
18
D of the upper surface of the second metal feature
18
for serving as a contact pad. Metal plug
22
filling through-hole
21
and constituting a second electrically conductive via
23
is formed similarly to first via
16
, i.e. by depositing a layer
24
of adhesion promoting and/or barrier material on the internal surface of through-hole
21
prior to filling with metal plug
22
.
As illustrated, a third metal feature
25
, formed of a composite of layers
25
A,
25
B, and
25
C analogous to layers
11
A,
11
B,
11
C,
18
A,
18
B,
18
C of the first and second metal features
11
and
18
, is then formed over fifth dielectric layer
20
and in electrical contact with metal plug
22
of via
23
which electrically connects the second and third metal features
18
and
25
.
The above-described process of metal feature formation, dielectric gap-filling, and via
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