Metal interconnection structure with dummy vias

Details Metal interconnection structure with dummy vias Metal interconnection structure with dummy vias

2001-03-21

2002-10-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S253000, C438S644000, C438S678000, C438S685000

Reexamination Certificate

active

06468894

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of metal interconnect formation for semiconductors, and more particularly to be the use of low k dielectric materials in metal interconnect structures.
BACKGROUND OF THE INVENTION
The escalating requirements for high-density and performance associated with ultra-large scale integration semiconductor wiring require responsive changes in interconnection technology. These escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by inter-wiring spacings. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontally with respect to the semiconductor substrate. Semiconductor chips comprising five or more levels of metalization are becoming more prevalent as device geometries shrink to sub-micron levels.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening in the dielectric layer by conventional photolithographic and etching techniques, and filling the opening with conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
In efforts to improve the operating performance of a chip, low k dielectric materials have been increasingly investigated for use as replacements for dielectric materials with higher k values. Lowering the overall k value of the dielectric layers employed in the metal interconnect layers lowers the RC of the chip and improves its performance. However, low k materials such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), SiOF, etc., are often more difficult to handle than traditionally employed higher k materials, such as an oxide. For example, low k dielectric materials are readily damaged by techniques used to remove photoresist materials after the patterning of a layer. Hence, a feature formed in a low k dielectric layer may be damaged when the photoresist layer used to form the feature (e.g., trench or via) is removed.
One of the problems with low k materials is the relatively low mechanical strength of such materials. This low mechanical strength makes the low k material susceptible to delamination, and scratching during chemical mechanical polishing (CMP). It has been found that those areas of a low k dielectric layer that have a greater copper density are more resistant to delamination and scratching.
This is a particular problem in via layers, which normally have a relatively low copper pattern density. Hence, via layers typically exhibit the highest tendency for delamination. This causes the metal interconnection layers to be poorly formed, leading to possible failure of the device.
SUMMARY OF THE INVENTION
There is a need for a metal interconnect structure and method of making the same that employs low k dielectric materials in a via layer, but has a reduced tendency for delamination and increased resistance to scratching during chemical mechanical polishing.
This and other needs are met by embodiments of the present invention which provide a method of forming metal interconnect layers comprising the steps of forming a low k dielectric layer on a substrate that contains a first metal line. A plurality of vias are formed in the low k dielectric layer. A second metal line is formed in the low k dielectric layer. A first set of the plurality of vias are connected between the first and second metal lines. A second set of the plurality of vias are not connected between the first and second metal lines.
By providing a second set of vias that are not connected (i.e. dummy vias) between the first and second metal lines in a low k dielectric layer, the metal pattern density in the via layer is increased.
This makes the via layer more resistant to delamination and scratching to reduce defects caused by these concerns.
In certain embodiments, the plurality of vias and the second metal line are formed in a single damascene manner, while in other embodiments the plurality of vias and the second metal line are formed in a dual damascene manner.
The earlier stated need is also met by other embodiments of the present invention which provide a metal interconnect arrangement comprising a first metal layer containing first metal lines. A low k dielectric layer is provided on the first metal layer. A plurality of vias are in the low k dielectric layer. A first set of the vias electrically contact at least one of the first metal lines. A second set of the vias do not electrically contact any of the first metal lines. A second metal layer is provided on the low k dielectric layer. This second metal layer contains second metal lines. At least some of the plurality of vias electrically contact only one of the first or second metal lines.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 6271084 (2001-08-01), Tu et al.

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