Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-31
2002-12-17
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S360000, C257S546000, C257S328000, C257S342000, C257S339000
Reexamination Certificate
active
06495888
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device provided with a p-n junction diode and a method of forming the same, and more particularly to a semiconductor device having both a metal oxide semiconductor field effect transistor and a p-n junction diode for protecting the transistor.
The semiconductor device having the MOS field effect transistor is provided with a p-n junction diode for preventing the MOS field effect transistor particularly a gate insulation film from being broken due to electrostatic discharge or a surge current and a surge voltage. It had been known that this semiconductor device is fabricated as follows.
FIGS. 1A and 1B
are fragmentary cross sectional elevation views illustrative of a semiconductor device provided with both a metal oxide semiconductor: field effect transistor and a p-n junction diode in sequential steps involved in the conventional fabrication method. The semiconductor device has a metal oxide semiconductor field effect transistor region
121
and a p-n junction diode region
122
.
With reference to
FIG. 1A
, an n
+
-type epitaxial layer
102
is formed on a top surface of a silicon substrate
101
. An n
−
-type well region
103
is selectively formed in an upper region of the n
+
-type epitaxial layer
102
. Device isolation layers
106
are selectively formed in upper regions of the n
−
-type well region
103
so that the device isolation layers
106
define both a metal oxide semiconductor field effect transistor region
121
and a p-n junction diode region
122
. The metal oxide semiconductor field effect transistor region
121
comprises a part of the n-type well region
103
surrounded by the device isolation layers
106
. The p-n junction diode region
122
also comprises another part of the n
−
-type well region
103
surrounded by the device isolation layers
106
.
In the metal oxide semiconductor field effect transistor region
121
, a gate insulation film
108
is selectively provided on the top surface of the n
−
-type well region
103
. A gate electrode
107
is provided on the gate insulation film
108
. A pair of p
−
-type lightly doped diffusion regions
113
a
and
113
b
are selectively formed in upper regions of the n
−
-type well region
103
by a self-alignment technique. Side wall insulation films
105
a
and
105
b
are formed on side walls of the gate electrode
107
.
With reference to
FIG. 1B
, an ion-implantation process is then carried out by use of the gate electrode
107
and the side wall insulation films
105
a
and
105
b
as masks for selectively introducing a p-type impurity into both the metal oxide semiconductor field effect transistor region
121
and the p-n junction diode region
122
. As a result, in the metal oxide semiconductor field effect transistor region
121
, source and drain p+-type diffusion regions
104
a
and
104
b
are selectively formed in the n
−
-type well region
103
so that the source and drain p+-type diffusion regions
104
a
and
104
b
are self-aligned to the gate electrode
107
and the side wall insulation films
105
a
and
105
b
, whereby lightly doped diffusion regions
113
a
and
113
b
remain only under the side wall insulation films
105
a
and
105
b
. The source and drain p+-type diffusion regions
104
a
and
104
b
are deeper than the lightly doped diffusion regions
113
a
and
113
b
. Concurrently, in the p-n junction diode region
122
, a p+-type region
104
c
is selectively formed in the n
−
-type well region
103
. The p+-type region
104
c
is defined by the device isolation layers
6
. The p+-type region
104
c
has the same depth as the source and drain p+-type diffusion regions
104
a
and
104
b
. In the metal oxide semiconductor field effect transistor region
121
, a source region comprises the p+-type diffusion region
104
a
and the lightly doped-diffusion region
113
a
, whilst a drain region comprises the p+-type diffusion region
104
b
and the lightly doped diffusion region
113
b
. In the p-n junction diode region
122
, the p+-type region
104
c
and the n
−
-type well region
103
form a p-n junction diode which has a p-n junction formed on an interface between the p+-type region
104
c
and the n
−
-type well region
103
.
Even illustrative is omitted, an inter-layer insulator is further formed entirely which extends over both the metal oxide semiconductor field effect transistor region
121
and the p-n junction diode region
122
. The inter-layer insulator not illustrated extends over the device isolation layers
106
, the side wall insulation films
105
, the gate electrode
107
and the source and drain p+-type diffusion regions
104
a
and
104
b
as well as over the p
+
-type region
104
c
. Contact holes not illustrated are formed in the inter-layer insulator so that the contact holes reach the gate electrode
107
and the source and drain p
+
-type diffusion regions
104
a
and
104
b
as well as the p
+
-type region
104
c
respectively. Metal plugs and metal interconnections not illustrated are formed, wherein the metal plugs are formed in the contact holes so that the metal plugs are in contact with the gate electrode
107
and the source and drain p
+
-type diffusion regions
104
a
and
104
b
as well as the p
+
-type region
104
c
, whilst the metal interconnections extend over the inter-layer insulator whereby the metal interconnections are electrically connected through the metal plugs in the contact holes to the gate electrode
107
and the source and drain p
+
-type diffusion regions
104
a
and
104
b
as well as the p
+
-type region
104
c.
In accordance with the conventional method of forming the semiconductor device, a distance “d” of the p-n junction of the diode or the interface between the p+-type region
104
c
and the n
−
-type well region
103
from a bottom of the n
−
-type well region
103
or an interface between the n
−
-type well region
103
and the n+-type epitaxial layer
102
depends on a difference of a depth of the n
−
-type well region
103
from a depth of the p+-type region
104
c
. The p+-type region
104
c
serves as an anode of the p-n junction diode. The p+-type region
104
c
is formed in the p-n junction diode region
122
by the same ion-implantation process for forming the source and drain p+-type diffusion regions
104
a
and
104
b
in the metal oxide semiconductor field effect transistor region
121
. Namely, the depth of the p+-type region
104
c
in the p-n junction diode region
122
is the same as the depth of the source and drain p+-type diffusion regions
104
a
and
104
b
in the metal oxide semiconductor field effect transistor region
121
. The depth of the p+-type region
104
c
in the p-n junction diode region
122
is decided by the depth of the source and drain p+-type diffusion regions
104
a
and
104
b
in the metal oxide semiconductor field effect transistor region
121
. The depth of the source and drain p+-type diffusion regions
104
a
and
104
b
and the depth of the n
−
-type well region
103
are also decided in consideration of the required dimensions and performances of the metal oxide semiconductor field effect transistor formed in the metal oxide semiconductor field effect transistor region
121
. Namely, the distance “d” in the p-n junction diode region
122
is decided depending upon the required dimensions and performances of the metal oxide semiconductor field effect transistor formed in the metal oxide semiconductor field effect transistor region
121
. A breakdown voltage of the p-n junction diode formed between the p+-type region
104
c
and the n
−
-type well region
103
depends upon the distance “d” in the p-n junction diode region
122
. Namely, the breakdown voltage of the p-n junction diode in the p-n junction diode region
122
is decided depending up
Lee Eddie
NEC Corporation
Nguyen Joseph
Young & Thompson
LandOfFree
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