Semiconductor memory integrated circuit operating at...

Details Semiconductor memory integrated circuit operating at... Semiconductor memory integrated circuit operating at...

2001-04-13

2002-11-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S230030, C365S230080

Reexamination Certificate

active

06483760

ABSTRACT:

BACKGROUND
Manufacturing of semiconductor integrated circuits includes various processes such as design, wafer fabrication, packaging, and test. Test of the semiconductor integrated circuits are performed before or after the packaging, depending on whether the test is a parameter test or a burn-in test. The parameter test determines before the packaging whether each fabricated integrated circuit is good or not. Only those integrated circuits that passed the parameter test are packaged and burn-in tested.
A fixed probe board for testing semiconductor integrated circuit chips is disclosed in U.S. Pat. No. 4,563,640 entitled “FIXED PROBE BOARD”, which is incorporated herein by reference in its entirety. The probe board includes multiple probe needles (or pins) mounted on a support base. The probe pins correspond to pads on a chip, such as data input/output pads, control signal pads, address pads, and command pads. The probe board disclosed in the '640 patent cannot test a number of integrated circuit chips simultaneously. Hereinafter, simultaneous testing of multiple integrated circuit chips is referred to as “a parallel test”.
In order to perform the parallel test, the number and allocation of the probe pins must be controlled to increase the number of integrated circuit chips tested simultaneously. The number of probe pins is limited within a probe board (or probe card) due to physical and manufacturing limitations of the probe card. If the number of pads on each integrated circuit chip increases and if the probe pins contact all of the pads, the number of integrated circuit chips tested simultaneously will decrease. That is, the number of probe pins allocated to each integrated circuit chip must be reduced to test as many semiconductor integrated circuit chips as possible at the same time.
For reducing the time spent for test and therefore, the manufacturing cost of integrated circuits, it is desirable to increase the number of semiconductor integrated circuit chips simultaneously tested by effectively allocating the probe pins.
SUMMARY
An embodiment of the present invention provides a semiconductor integrated circuit that can enable effective test thereof. The semiconductor integrated circuit includes: a memory cell array having multiple banks; a row selection circuit that selects one of the banks and a row of each of the array blocks in the selected bank; a read circuit that reads test data from the selected bank; a parallel test control circuit; a bit organization address control circuit; and a parallel test circuit.
The parallel test control circuit, in response to a wafer test flag signal, a package test flag signal, and a bank activation signal, generates a first control signal and a second control signal. The bit organization address control circuit, in response to the wafer test flag signal, the package test flag signal, the bank activation signal, and a bit organization information signal, generates a third control signal. The parallel test circuit, in response to the first and second control signals, determines whether all bits of the test data read have the same logic levels. The first, second, and third control signals determines where the test data are read from in the memory cell array.
The semiconductor integrated circuit further includes a mode register set circuit and an address buffer circuit. The mode register set circuit outputs the wafer test flag signal, the package test flag signal, and the bank activation signal. The address buffer circuit receives the first, second, and third control signals, and an address signal, and determines whether the address signal is used in determining where the test data are read from in the memory cell array. In addition, the parallel test circuit has a plurality of first to third comparators.


REFERENCES:
patent: 4563640 (1986-01-01), Hasegawa
patent: 5072138 (1991-12-01), Slemmer et al.
patent: 5134587 (1992-07-01), Steele
patent: 5706232 (1998-01-01), McClure et al.
patent: 5864565 (1999-01-01), Ochoa et al.
Betty Prince, “High Performance Memories, New architecture DRAMs and SRAMs evolution and function,” (1999) pp. 152-154.

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