Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-09-14
2002-08-13
Bragdon, Reginald G. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S217000
Reexamination Certificate
active
06434658
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more specifically, to a memory device having a flash memory.
2. Description of the Background Art
In recent years, with the advance of the semiconductor manufacture technology, storage capacities of flash memories have become increasingly larger. With the increase in the storage capacity, the use of a memory device having a flash memory as a storage medium being advantageously small in size and low in power consumption has gradually been accepted particularly in the field of portable equipment.
A flash memory is a non-volatile, rewritable semiconductor memory device that allows the erase operation of data one section at a time. The flash memory integrates storage elements at a high density, and, in order to enable a fast-speed data transmission and reception, specifies a sector address, and reads, erases, and writes (programs) a certain amount of data one sector at a time. In the present specification, the term “program” refers to setting the state of a memory cell in a flash memory to correspond to the value of either 1 or 0 according to data provided from outside. As the capacity of the flash memory increases in size, the sector capacity, the unit of data the flash memory reads out at one time, tends to increase in size as well. For instance, in an AND-type flash memory of 256 Mbits, the sector capacity is 2048 bytes.
On the other hand, the data capacity (hereinafter referred to as a medium sector capacity), which is a unit of data the informational equipment such as a personal computer transmits to and receives from a memory device such as a hard disk or a memory card, is normally 512 bytes, for example, and no such tendency to increase in the medium sector capacity is noted in particular.
In such a memory device having a flash memory with a sector structure, it is necessary to incorporate into the memory device a buffer memory for temporarily storing sector data of a flash memory and for adjusting the timing and the capacity for the data transfer between the memory device and the host system. Normally, an SRAM (Static Random Access Memory) or the like is used as the buffer memory.
The buffer memory was required to be have a capacity of the same or a larger size than the sector capacity of the flash memory even when the capacity of data transfer between the memory device and the host system, i.e. the medium sector capacity, was smaller than the sector capacity of the flash memory.
The sector capacity of the flash memory, however, is on the increase every year so that the incorporation of an SRAM of a large capacity is required, which is a disadvantage with respect to the cost.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory device having a flash memory that allows the incorporation of a buffer memory of a small capacity equivalent to the medium sector capacity as well as the reduction in cost.
In summary, the present invention is a memory device with a flash memory and having a write mode in which data is stored upon the reception of an external write address signal and an external write data train from a host system, and including a flash memory and a data input/output portion.
In the flash memory, in the data erase operation, a memory region holding a prescribed number of bits of data is erased at one time as the smallest unit, and in the write mode an internal write data train having a prescribed data length is written according to an internal write address signal.
In the write mode, the data input/output portion receives the external write address signal and generates an internal write address signal, receives and retains the external write data train, and outputs the internal write data train based on the external write data train and the external write address signal.
The data input/output portion includes a first interface portion, a buffer memory, and a second interface portion.
The first interface portion receives the external write data train and the external write address signal from the host system in the write mode.
The buffer memory has a storage capacity corresponding to data elements not smaller in number than data elements contained in the external write data train and smaller in number than data elements contained in the internal write data train. In the write mode, the buffer memory receives the external write data train from the first interface portion.
In the write mode, the second interface portion receives the external write address signal from the first interface portion and generates the internal write address signal, adds to the external write data train read out from the buffer memory dummy data which does not cause data overwrite in the memory region according to the external write address signal to generate the internal write data train.
According to another aspect of the present invention, a memory device having a flash memory is provided which receives an external address signal from a host system and communicates an external data train when storing data, and which includes a data input/output portion and a flash memory.
The data input/output portion generates an internal main address and an internal sub-address corresponding to an external address.
In the flash memory, a memory region holding a prescribed number of bits of data is erased at one time as the smallest unit in the data erase operation, the internal main address selects a memory region as a unit, the internal sub-address specifies a data transmission and reception start location within the memory region, and an internal data train containing a plurality of data elements can be received and transmitted.
The storage capacity of the memory region is larger than the storage capacity corresponding to the number of data elements contained in the external data train.
The data input/output portion adds to a lead address of the memory region a number corresponding to the non-negative integer multiple of the number of data elements contained in the external write data train to produce the internal sub-address.
Thus, the main advantage of the present invention is that, when a flash memory for sector reading is used as a semiconductor device for data storage, the incorporation of a small-capacity buffer memory is advantageous with respect to the cost.
Other advantages of the present invention are that the incorporation of a small-capacity buffer memory is advantageous with respect to the cost, and that data rewrite per medium sector is possible.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5627783 (1997-05-01), Miyauchi
patent: 5724285 (1998-03-01), Shinohara
patent: 5765002 (1998-06-01), Garner et al.
patent: 5905993 (1999-05-01), Shinohara
patent: 5963474 (1999-10-01), Uno et al.
patent: 10-207726 (1998-08-01), None
Bragdon Reginald G.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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