Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-02-26
2002-06-25
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S311000, C438S455000, C438S459000, C438S977000
Reexamination Certificate
active
06410371
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor-on-insulator (SOI) integrated circuits and, more particularly, to an SOI wafer having a Si/SiGe/Si active layer and a method of fabricating the SOI wafer using a wafer bonding process.
BACKGROUND ART
Traditional semiconductor-on-insulator (SOI) integrated circuits typically have a silicon substrate having a buried oxide (BOX) layer disposed thereon. A silicon active layer is disposed on the BOX layer. Within the active layer, active devices, such as transistors, are formed in active regions. The size and placement of the active regions are defined by isolation regions. As a result of this arrangement, the active devices are isolated from the substrate by the BOX layer. More specifically, a body region of each SOI transistor does not have body contacts and is therefore “floating.”
SOI chips offer potential advantages over bulk chips for the fabrication of high performance integrated circuits for digital circuitry. Such digital circuitry is typically made from partially-depleted metal oxide semiconductor field effect transistors (MOSFETs). In such circuits, dielectric isolation and reduction of parasitic capacitance improve circuit performance, and virtually eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and the packing density greatly increased.
However, the mobility of the carriers (i.e., electrons or holes) within the silicon of the active layer, and primarily in a channel portion of the body region, is limited. Therefore, there exists a need in the art to increase the mobility of the carriers within the channel of SOI devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer.
According to another aspect of the invention, the invention is a semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate; a buried oxide. (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer having an upper silicon layer disposed on a silicon-germanium layer, the silicon-germanium layer disposed on a lower silicon layer, wherein the silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.
REFERENCES:
patent: 5234535 (1993-08-01), Beyer et al.
patent: 5438015 (1995-08-01), Lur
patent: 5461243 (1995-10-01), Ek et al.
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5583059 (1996-12-01), Burghartz
patent: 5683934 (1997-11-01), Candeleria
patent: 5686735 (1997-11-01), Sim
patent: 5714777 (1998-02-01), Ismail et al.
patent: 5847419 (1998-12-01), Imai et al.
patent: 5849627 (1998-12-01), Linn et al.
patent: 5906951 (1999-05-01), Chu et al.
patent: 5963817 (1999-10-01), Chu et al.
patent: 5998807 (1999-12-01), Lustig et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6153495 (2000-11-01), Kub et al.
An Judy Xilin
En William G.
Riccobene Concetta E.
Yu Bin
Advanced Micro Devices , Inc.
Pham Long
Renner , Otto, Boisselle & Sklar, LLP
LandOfFree
Method of fabrication of semiconductor-on-insulator (SOI)... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabrication of semiconductor-on-insulator (SOI)..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabrication of semiconductor-on-insulator (SOI)... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2929926