Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-05-04
2002-08-20
Sheikh, Ayaz (Department: 2155)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S038110, C714S704000, C369S084000, C360S015000, C360S032000
Reexamination Certificate
active
06438715
ABSTRACT:
FIELD OF THE INVENTION
The invention is related to the field of disk drives, and in particular, to the addition of tracing logic into a drive control integrated circuit.
Problem
A disk drive stores user data on a disk device. The disk drive includes a drive control integrated circuit that controls the transfer of data between the user and the disk device. The drive control integrated circuit also controls the positioning of heads in the disk device to read and write the data to the proper locations on the disks. When the data is written to the disk device, the drive control integrated circuit obtains the data from the user, positions the appropriate head, and transfers the data to the disk device. When the data is subsequently read, the drive control integrated circuit re-positions the appropriate head, obtains the data from the disk device, and transfers the data to the user.
System designers analyze the operation of the drive control integrated circuit to correct errors and optimize performance. The operation of circuitry is analyzed by monitoring points in the circuitry to identify the information flowing between circuit elements. The acquisition of this operational information from a circuit is called tracing. For example, it is important to trace the sequence of instructions that are executed in the drive control integrated circuit in response to particular conditions. The sequence of instructions is traced by monitoring the instruction addresses and program data that are present on the address bus.
In the past, the drive control integrated circuit consisted of multiple integrated circuits connected by an external bus. System designers performed tracing operations by simply connecting a logic analyzer or circuit emulator to the external bus. As technology has advanced, the integrated circuits have been combined into a single drive control integrated circuit with an internal bus. The use of a logic analyzer or circuit emulator is no longer practical since the bus has been incorporated into the integrated circuit and is not available for convenient external connection.
One prior solution to this problem is disclosed in U.S. patent application No, 08/997130 entitled “Hardware Tracing/Logging For Highly Integrated Embedded Controller Device”, filed on Dec. 23, 1997, and that is hereby incorporated by reference into this application. The prior solution adds trace logic to the drive control integrated circuit to monitor internal operations. The trace logic identifies data and address information from the internal bus and stores this information in a memory. The system designers then retrieve the data and address information from the memory to study the operation of the drive control integrated circuit.
The prior solution allows the system designers to select particular data and address information for detection and storage in the memory. In a typical trace operation, the data and address information can quickly exceed the capacity of the memory allocated for the trace. The data and address information is then either overwritten or the trace is stopped. In addition, a complex listing of data and address information is difficult to analyze for program flow and important operational parameters. Disk drives would be improved by technology that provided a more intelligent and efficient tracing capability within the drive control integrated circuit.
Solution
The invention solves the above problem by providing a drive control integrated circuit with an intelligent and efficient tracing capability. The drive control integrated circuit executes operating instructions that are grouped into modules. The drive control integrated circuit stores the module numbers for the executed modules in a memory. System designers can then retrieve the module numbers from the memory to assess the operation of the drive control integrated circuit. Some typical modules are read, write, seek, track follow, error, and other servo modules. The drive control integrated circuit also stores operating parameters associated with the executed modules in the memory. Some typical operating parameters are instruction codes, head numbers, cylinder numbers, and error codes.
A processor in the drive control integrated circuit executes the modules. Each module includes a trace macro that expands to a set of instructions. The instructions direct the processor to move the module number and associated operating parameters to storage locations. The storage locations could be registers on the processor bus. A trace controller in the drive control integrated circuit obtains the module number and associated operating parameters from the storage locations. The trace controller starts and stops the transfer of the module numbers and operating parameters based on the module numbers in the storage locations. Alternatively, the trace controller starts and stops the transfer of the module numbers and operating parameters based on addresses from the processor bus. The trace controller also includes a data filter that selects particular module numbers for storage in the memory along with their associated operating parameters.
Advantageously, the invention allows system designers to specify a particular trace operation and wait for the drive control integrated circuit to load the module numbers and operational parameters of interest into the memory. The use of selected module numbers and operating parameters reduces the amount of data typically stored in conventional trace operation. The reduction in data increases the available bandwidth for access to the memory. The reduction in data also allows a detailed trace without filling up the memory allocated for the trace.
Since arbitration is used to allow the trace controller to access the memory, the trace operation is effectively transparent to system performance. In addition, the processor only executes an additional trace macro in each module to support the trace. The effect of the trace operation on the processor is negligible. Therefore, the invention provides programmable and efficient tracing without influencing real-time system performance. This lack of impact allows for accurate system evaluation under realistic operating conditions.
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Jean Frantz B.
Jorgenson Lisa K.
Kubida William J.
Sheikh Ayaz
STMicroelectronics N.V.
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