Modular implementation for a parallelized key equation solver fo

Details Modular implementation for a parallelized key equation solver fo Modular implementation for a parallelized key equation solver fo

1993-09-27

1995-06-27

Baker, Stephen M.

Excavating

H03M 1300

Patent

active

054286280

ABSTRACT:
Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. Circuitry implements two computation sequences. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two sequences being required to decode t symbols in error. These sequences are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in the other sequence being paired with a multiplication operation in the next iteration of the one sequence. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed. Two consecutive executions of the other sequence are prevented.

REFERENCES:
patent: 4845713 (1989-07-01), Zook
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Blahut, R., Theory and Practice of Error Control Codes, Addison-Wesley Publishing Co., 1984, pp. 183-191.
Whiting, D., Bit-Serial Reed-Solomon Decoders in VLSI, PhD Thesis, California Institute of Technology, Pasadena, 1984, pp. 62-68, 104.
E. R. Berlekamp, "Algebraic Coding Theory", McGraw-Hill, 1968, pp. 178-199.
J. L. Massey, "Shift-Register Synthesis and BCH Decoding", IEEE Transactions on Information Theory, vol. IT-15, No. 1, Jan. 1969, pp. 122-127.
K. Y. Liu, "Architecture for VLSI Design of Reed-Solomon Decoders", IEEE Transactions on Computers, Feb. 1984, pp. 178-189.
R. T. Chien, "Cyclic Decoding Procedures for Bose-Chaudhuri-Hocquenghem Codes", IEEE Transactions on Information Theory-10, Oct. 1964, pp. 357-363.

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