Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-12-10
2002-08-27
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S378000, C257S412000
Reexamination Certificate
active
06441441
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a bipolar complementary metal-oxide semiconductor device (hereinafter referred to as a “Bi-CMOS device”) and a method of manufacturing the same.
2. Description of the Background Art
FIG. 23
is a cross-sectional structural view of a conventional Bi-CMOS device. As shown in the figure, the conventional Bi-CMOS device is constructed so that an NPN bipolar transistor, a P-channel MOS transistor, and an N-channel MOS transistor are formed on a P-type semiconductor substrate
1
.
The NPN bipolar transistor includes a heavily doped N-type buried layer
2
formed in the lightly doped P-type semiconductor substrate
1
, a lightly doped N-type collector layer
3
, a heavily doped N-type contact collector layer
4
, a P-type isolating layer
7
, a heavily doped P-type outer base layer
8
, a moderately doped P-type base layer
9
, a heavily doped N-type emitter layer
10
, a base electrode
200
, and an emitter electrode
301
. The NPN bipolar transistor further includes an element isolating oxide film
101
, an oxide film
104
, a thermal oxide film
105
, a sidewall oxide film
106
, and an oxide film
107
. The emitter electrode
301
is formed with a polycrystalline silicon film in which arsenic is generally introduced as an N-type impurity.
The P-channel MOS transistor includes a lightly doped N-type well layer
5
formed in the P-type semiconductor substrate
1
, a heavily doped P-type source/drain layer
11
, a gate oxide film
102
, an oxide film
107
, and a gate electrode
401
. Here, the gate electrode
401
is formed with upper and lower polycrystalline silicon films
502
and
501
in which arsenic is generally introduced as an N-type impurity. The upper polycrystalline silicon film
502
is the same film as the emitter electrode
301
of the NPN bipolar transistor.
The N-channel MOS transistor includes a lightly doped P-type well layer
6
formed in the P-type semiconductor
1
, a heavily doped N-type source/drain layer
12
, a gate oxide film
102
, an oxide film
107
, and a gate electrode
402
. Here, the gate electrode
402
is formed with the same upper and lower polycrystalline silicon films
502
and
501
as the gate electrode
401
of the P-channel MOS transistor.
The NPN bipolar, P-channel MOS, and N-channel MOS transistors are isolated from one another by the element isolating oxide films
101
, and each transistor surface is covered with an oxide film
108
, in which contact holes
601
,
602
,
603
,
606
, and
607
and a metal wire
700
are formed.
Next,
FIG. 24
is a cross-sectional structural view showing one step of the method of manufacturing the conventional Bi-CMOS device. The method of manufacturing the conventional Bi-CMOS device will be described with reference to
FIGS. 23 and 24
.
In the conventional manufacturing method, a heavily doped N-type buried layer
2
is first formed in the NPN bipolar transistor formation region of the lightly doped P-type semiconductor substrate
1
, and then a lightly doped N-type epitaxial layer
3
is grown on the entire surface. Thereafter, the element isolating oxide film
101
is formed on each element isolating region and across the collector and base layer of the bipolar transistor. Subsequently, the heavily doped N-type collector layer
4
of the NPN bipolar transistor is formed on a collector contact portion, and the lightly doped N-type well layer S of the P-channel MOS transistor, and the lightly doped P-type well layer
6
of the N-channel MOS transistor are formed, respectively. Furthermore, a moderately doped P-type isolating layer
7
is formed in the N-type epitaxial layer
3
and between the N-type epitaxial layer
3
and the N-type well layer
5
. Note that the N-type epitaxial layer
3
becomes the N-type collector layer
3
of the NPN bipolar transistor.
Next, a gate oxide film
102
is formed on each surface of the N-type collector layer
3
, the N-type collector contact layer
4
, the N-type well layer
5
, and the P-type well layer
6
. Further, a lower polycrystalline silicon film
501
is formed on the entire surface of the gate oxide film
102
.
Next, the lower polycrystalline silicon film
501
and the gate oxide film
102
on the surface of the N-type collector
3
are removed, and a polycrystalline silicon film
500
is formed on the entire surface. Then, boron ions are implanted into the polycrystalline silicon film
500
so that it becomes a P-type.
Next, an oxide film
104
is formed on the entire surface of the polycrystalline silicon film
500
. The oxide film
104
and the polycrystalline silicon film
500
are removed in sequence, while the films
104
and
500
, deposited on the outer base layer formation region of the NPN bipolar transistor and on a portion of the element isolating oxide film
101
, are not removed. Next, a thermal oxide film
105
is formed on the surface of the N-type collector
3
from which the polycrystalline silicon film
500
has been removed, and at the same time, a heavily doped P-type outer base layer
8
is formed by thermal diffusion of boron from the polycrystalline silicon film
500
into the N-type collector layer
3
. Here, the polycrystalline silicon film
500
becomes the base electrode
200
of the NPN bipolar transistor. Further, boron ions are implanted through the thermal oxide film
105
to form a moderately doped P-type base layer
9
on the upper portion of the N-type collector layer
3
.
Next, an oxide film is deposited on the entire surface, and side-wall oxide films
106
are formed on side surfaces of the base electrode
200
and the oxide film
104
by etching back the deposited oxide film. At this time, the thermal oxide film
105
is removed by over-etching.
Next, an upper polycrystalline silicon film
502
is formed on the entire surface, as shown in
FIG. 24
, and arsenic ions are implanted into the upper polycrystalline silicon film
502
and then annealing is performed. Then, arsenic is diffused from the upper polycrystalline silicon film
502
into the upper portion of the P-type base layer
9
to form a heavily doped N-type emitter
10
. Simultaneously, arsenic is diffused into the lower polycrystalline silicon film
501
so that it becomes a N-type.
Furthermore, an oxide film
107
is deposited over the entire surface of the upper polycrystalline silicon film
502
. As shown in
FIG. 23
, the oxide film
107
, the upper polycrystalline silicon film
502
, and the lower polycrystalline silicon film
501
are sequentially removed, while those on the emitter electrode formation region of the NPN bipolar transistor and the gate electrode formation regions of the MOS transistors are not removed. In this way, the emitter electrode
301
, consisting of the upper polycrystalline silicon film
502
, and the gate electrodes
401
and
402
, consisting of the upper and lower polycrystalline silicon films
502
and
501
, are formed. During these processes, the gate oxide film
102
serves as a protective film for each surface of the N-type collector contact layer
4
, the N-type well layer
5
, and the P-type well layer
6
.
Next, the NPN bipolar transistor and the N-channel MOS transistor are covered with a photoresist film (not shown), and boron ions are implanted through the gate oxide film
102
to form a heavily doped P-type source/drain layer
11
on the upper portion of the N-type well layer
5
, as shown in FIG.
23
. When the ion implantation is performed, the oxide film
107
serves as a mask for the gate electrode
401
. Next, the NPN bipolar transistor and the P-channel MOS transistor are covered with a photoresist film (not shown), and arsenic ions are implanted through the gate oxide film
102
to form a heavily doped N-type source/drain layer
12
on the upper portion of the P-type well layer
6
. When the ion implantation is performed, the oxide film
107
serves as a mask for the gate electrode
402
. Further, the P-type source/drain layer
11
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Prenty Mark V.
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