Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – With physical configuration of semiconductor surface to...
Reexamination Certificate
2001-11-28
2002-11-05
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
With physical configuration of semiconductor surface to...
C257S336000, C257S337000, C257S339000, C257S341000, C257S488000, C257S492000, C257S493000, C257S494000
Reexamination Certificate
active
06476458
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, specially, to a structure capable of withstanding high voltage at an periphery of the semiconductor device.
2. Related Art
As shown in
FIG. 7
, a guard ring
100
is formed around an element region, which has a structure of RESURF in which a semiconductor region corresponding to the guard ring
100
is perfectly depleted before a breakdown occurs. It is found that even if such a epitaxial layer is employed, which has a thickness of such a degree that a design margin is very restricted, the guard ring has a characteristic of high withstand voltage in comparison with a region where transistors are formed when employing the guard ring
100
.
However, it is also found that such a problem may occur that when a p-well
200
, which is formed to draw holes generated at a periphery portion and is not perfectly depleted in occurring the breakdown, is formed between the guard ring
100
and a transistor-cell region (element region), a withstand voltage at a boundary between the guard ring
100
and the p-well
200
(A
1
in
FIG. 7
) is lowered in rising a potential at a drain region.
SUMMARY OF THE INVENTION
This invention has been conceived in view of the background as described above and an object of the invention is to provide a semiconductor device capable of enhancing a withstand voltage at a peripheral region around an element in comparison with a withstand voltage at the element.
When a voltage applied to the element (a voltage applied between a source and a drain in a case where the element is a MOS transistor) is rising, as described above, an electric field increases at an edge of a well region (p-well) in FIG.
7
. This phenomenon deeply relates to a fact that a radius r
1
at an edge of a carrier remaining region which is not depleted in the well region is small.
Therefore, the inventor of the present invention supposed that a withstand voltage at a boundary between adjacent regions with each other is prevented from being lowered by enlarging the radius, or curvature at the boundary so as to decrease the electric field.
According to a first aspect of the present invention, at a periphery of an element region formed in a substrate having a first conductive type, an impurity diffused region having a second conductive type is formed as a guard ring, and a connecting region, which has high impurity concentration in comparison with the impurity diffused region and has the same conductive type as the impurity diffused region, is formed adjacent to the impurity diffused region so as to make a boundary with the impurity diffused region. Incidentally, the impurity diffused region and the connecting region are formed in the substrate so as to form pn junctions. Moreover, a step arrangement is formed at a region where the impurity diffused region is formed so that the connecting region is terminated at an edge of the step arrangement. When reverse bias is applied to the pn junctions, a depletion layer is expanded in the impurity diffused region and the connecting region, which defines a carrier remaining region in the connecting region. Moreover, before the reverse bias becomes high to such a degree that the element region breaks down, the impurity diffused region is completely depleted. By employing this structure, a curvature of the carrier remaining region that is defined by the depletion layer is enlarged so that electric field is prevented from increasing at a boundary between the depletion layer and the carrier remaining region.
According to another aspect of the present invention, an impurity diffused region, a connecting region, a step arrangement are formed as described above. Moreover, when the impurity diffused region is fully depleted, a depletion layer expands in the connecting region so that a part of the connecting region remains as a carrier remaining region that has carriers therein, whereby a boundary is formed between the depletion layer and the carrier remaining region in the connecting region. Specifically, the boundary is terminated at a contour of the step arrangement.
Preferably, when such a reverse bias that the impurity diffused region is completely depleted is applied, the boundary formed between the depletion layer and the carrier remaining region in the connecting region is disposed higher than the impurity diffused region, and is terminated at a wall portion of the step arrangement.
REFERENCES:
patent: 4805004 (1989-02-01), Gandolfi et al.
patent: 5557127 (1996-09-01), Ajit et al.
patent: 6054748 (2000-04-01), Tsukada et al.
patent: 6313504 (2001-11-01), Furuta et al.
patent: A-2-98968 (1990-04-01), None
patent: A-8-78668 (1996-03-01), None
patent: A-8-255919 (1996-10-01), None
patent: A-8-306937 (1996-11-01), None
patent: A-9-246549 (1997-09-01), None
patent: A-10-173174 (1998-06-01), None
patent: A-10-321878 (1998-12-01), None
patent: A-11-68085 (1999-03-01), None
Denso Corporation
Law Offices of David G. Posz
Ngo Ngan V.
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