Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
1998-05-18
2002-06-25
Pham, Chi (Department: 2631)
Pulse or digital communications
Receivers
Angle modulation
C375S376000, C329S325000
Reexamination Certificate
active
06411660
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to frequency synthesizers for digital time division duplexing systems and, more specifically, to a device for reducing a lock-up time of a frequency synthesizer.
2. Description of the Related Art
A digital time division duplexing (hereinafter referred to as digital TDD) system such as a TDD cordless telephone includes a transmitter and receiver. Additionally, a frequency synthesizer is employed in order to generate an intermediate frequency (IF) signal efficiently. However, the lock-up time of the frequency synthesizer, which is the time required by the frequency synthesizer to switch from a transmission frequency to a reception frequency, affects generation of the IF signal. In the digital TDD cordless telephone, the transmitter is disabled in a reception mode, and the receiver is disabled in a transmission mode. In order to generate appropriate frequencies for the respective operational modes, the digital TDD cordless telephone has a signal processor consisting of a phase controlled oscillator. The phase controlled oscillator is switched at high speed for a guard time when the transmitter and the receiver are respectively disabled and enabled.
FIG. 1
is a block diagram of a conventional signal processor for a digital cordless telephone. The signal processor is divided into a transmitter, a receiver, and a frequency synthesizer
100
. The receiver is composed of a low noise amplifier (LNA)
4
, a first mixer
5
, a bandpass filter (BPF)
6
, an amplifier
7
, a second mixer
8
, a second bandpass filter
9
, a second amplifier
10
, a first local oscillator
24
, and a demodulator (not shown). The transmitter is composed of a local oscillating circuit
200
(consisting, itself, of a local oscillator
21
, a frequency multiplier
22
, and a bandpass filter
23
), a third mixer
13
, and two power amplifiers
14
and
15
. The frequency synthesizer
100
is connected between the first and third mixers
5
and
13
by way of buffers
11
and
12
, respectively. Additionally, the signal processor includes an antenna
1
, a bandpass filter
2
, a switch
3
, and a baseband filter (BBF)
20
for providing the frequency synthesizer
100
with digital data output from a central processing unit (not shown).
As illustrated, the signal processor has two separate local oscillators
21
and
24
generating the local oscillation frequencies for transmission and reception, respectively.
In the reception mode, a handset receives a radio signal transmitted from a base set (or base unit) through antenna
1
, and delivers the received radio signal to the receiver by way of bandpass filter
2
and switch
3
. In the transmission mode, the handset transfers a transmission frequency output from the transmitter to antenna
1
via switch
3
and the bandpass filter
2
.
In
FIG. 1
, an intermediate frequency f(IF) is identical to the local oscillation frequency f(LO) for transmission. Accordingly, in the reception mode, the local oscillation frequency f(LO) output from the transmitter affects the intermediate frequency f(IF) output from the first mixer
5
of the receiver, thereby lowering the receiving sensitivity. In order to prevent such a phenomenon, the local oscillating circuit
200
should be disabled during the reception mode. However, second local oscillator
21
of local oscillating circuit
200
, which is a crystal oscillator with high stability, has a very low switching speed and thus, cannot interlock with the other elements in the transmitter. Therefore, instead of disabling second local oscillator
21
to prevent the local oscillation frequency f(LO) from affecting the intermediate frequency f(IF), local oscillating circuit
200
includes a frequency multiplier
22
and a bandpass filter
23
, whereby the frequency multiplier
22
is disabled in the reception mode.
However, since the second local oscillator
21
continues to oscillate even in the reception mode, harmonic distortion signals are generated corresponding to the exponential frequency characteristic of semiconductor elements (e.g., transistors and diodes), which may be difficult to remove. Further, local oscillating circuit
200
requires LC bandpass filter
23
, which consists of an inductor (L) and a capacitor (C) to filter unwanted harmonic frequencies generated from frequency multiplier
22
. The inductor of bandpass filter
23
is relatively large in size and expensive, compared to the other elements. Additionally, the signal processor includes two separate local oscillators
24
and
21
for the receiver and the transmitter, respectively, which make the processor undesirably expensive and heavy.
FIG. 2
shows a block diagram of an improved conventional signal processor in the digital cordless telephone. The signal processor is an improvement over the processor of
FIG. 1
in that it employs fast frequency switching to switch from a transmission frequency to a reception frequency. However, as stated hereinbelow, the signal processor of
FIG. 2
is not without deficiency. For example, the lock-up time of the frequency synthesizer cannot be reduced to below 20 &mgr;sec. The improved signal processor includes baseband filter
20
, a frequency synthesizer
300
, and a switch
28
. The baseband filter
20
has an output terminal connected to frequency synthesizer
300
. An output terminal of frequency synthesizer
300
is connected to second mixer
8
and third mixer
13
via switch
28
, which is switchable according to the. desired operating mode. The other structures are the same as those of the processor of FIG.
1
.
FIG. 3
is a block diagram of the conventional frequency synthesizer
300
of FIG.
2
. The frequency synthesizer
300
includes a PLL IC (Phase Locked Loop Integrated Circuit)
25
, a voltage controlled oscillator
26
, and a loop filter
27
. The PLL IC
25
is composed of the following elements: a first frequency divider
25
a
for frequency dividing an output frequency f
0
of a reference frequency generator
16
by a divisor R; a phase comparator
25
b
for comparing an output frequency f
1
of first frequency divider
25
a
with a frequency f
2
to detect a phase difference therebetween; a charge pump
25
c
for controlling the charging and discharging of a capacitor in loop filter
27
in response to an output of phase comparator
25
b
; a pre-scaler
25
e
for frequency dividing an output frequency of voltage controlled oscillator
26
by a divisor P/(P+1); and a second frequency divider
25
d
for frequency dividing an output frequency of pre-scaler
30
by a divisor N to generate the frequency
12
to phase comparator
25
b
. The loop filter
27
, which is connected between voltage controlled oscillator
26
and an output terminal Do of charge pump
25
c
, shapes the output signal of the charge pump
25
c
. A channel selection signal Rx/Tx is applied to a divide ratio switching input terminal DIV of PLL IC
25
. The channel selection signal Rx/Tx sets the transmission and reception modes, and is provided from the central processing unit.
Referring back to
FIG. 2
, an output terminal of reference frequency generator
16
is connected to an input terminal of PLL IC
25
in frequency synthesizer
300
. The switches
3
and
28
are interlocked with each other, and are switchable according to the channel selection (or mode selection) signal Rx/Tx. Specifically, in the reception mode, movable contacts ‘a’ of switches
3
and
28
are switched to fixed contacts ‘b’, which are connected to the receiver. Further, in the transmission mode, the movable contacts ‘a’ are switched to fixed contacts ‘c’, which are connected to the transmitter. Accordingly, in the reception mode, an RF (Radio Frequency) signal captured by antenna
1
is delivered to low noise amplifier
4
through bandpass filter
2
, and in the transmission mode, a transmission signal output from power amplifier
15
is transmitted through antenna
1
. An output of frequency synthesizer
100
is amplified by buffers
11
and
12
and transferred to first
Dilworth & Barrese LLP
Pham Chi
Samsung Electronics Co,. Ltd.
Tran Khai
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