Semiconductor device having a constant-current source circuit

Details Semiconductor device having a constant-current source circuit Semiconductor device having a constant-current source circuit

2000-03-08

2002-04-23

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S031000, C326S032000

Reexamination Certificate

active

06377074

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, to a semiconductor device having an internal circuit that performs a prescribed operation based on a constant current generated by a constant-current source circuit.
2. Description of the Background Art
Conventionally, in a semiconductor integrated circuit device such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), or the like, a constant-current source circuit is provided that is less likely to be affected by variations of an external power-supply potential extVdd or by process variations (variations of a threshold voltage of an MOS transistor). The constant current generated by the constant-current source circuit is transmitted to various internal circuits via a current mirror circuit. Each internal circuit performs a prescribed operation based on the transmitted constant current. Thus, a semiconductor integrated circuit device that is less likely to be affected by variations of an external power-supply potential extVdd or by process variations is realized.
FIG. 14
is a block diagram representing the main portion of a conventional semiconductor integrated circuit device. In
FIG. 14
, the semiconductor integrated circuit device is provided with a constant-current source circuit
81
and a plurality (four in the figure) of internal circuits
82
to
85
.
Constant-current source circuit
81
includes resistance element
91
and
92
, a capacitor
93
, P-channel MOS transistors
94
and
95
, and N-channel MOS transistors
96
and
97
, as shown in FIG.
15
. Resistance element
91
and capacitor
93
are connected in series between an external power-supply potential extVdd line and a ground potential GND line, forming a low pass filter. MOS transistors
94
and
96
, resistance element
92
, and MOS transistors
95
and
97
are respectively connected in series between a node N
91
between resistance element
91
and capacitor
93
and a ground potential GND line. Gates of P-channel MOS transistors
94
and
95
are both connected to the drain of P-channel MOS transistor
94
. Gates of N-channel MOS transistors
96
and
97
are both connected to the drain of N-channel MOS transistor
97
. N-channel MOS transistors
96
and
97
together form a current mirror circuit.
The high frequency noise on an external power-supply potential extVdd line is removed by the low pass filter formed by resistance element
91
and capacitor
93
so that external power-supply potential extVdd devoid of the high frequency noise is provided to node N
91
. P-channel MOS transistors
94
and
95
are both set to operate in a sub-threshold region, and the current mirror circuit formed by N-channel MOS transistors
96
and
97
allows currents Ic of the same value to flow through P-channel MOS transistors
94
and
95
.
A gate width W
2
of P-channel MOS transistor
95
is set to be greater than a gate width W
1
of P-channel MOS transistor
94
so that a voltage difference dV is created between P-channel MOS transistors
94
and
95
in gate-source voltages Vgs required to allow currents Ic of the same value to flow through P-channel MOS transistors
94
and
95
. This voltage dV is ideally dV=k×T/q×1n(W
2
/W
1
). Here, k indicates the Boltzmann's constant, T indicates the absolute temperature, and q indicates the amount of charge of electrons. Therefore, dV is proportional to absolute temperature T. In addition, if the resistance value of resistance element
92
is indicated by R, then Ic=dV/R. Here, if the temperature dependency of R is negligible, Ic is proportional to absolute temperature T. Thus, the temperature characteristic of Ic is positive.
This Ic, being less likely to be affected by variations of an external power-supply potential extVdd or by process variations, is used in various internal circuits
82
to
85
within the semiconductor integrated circuit device. A gate potential of P-channel MOS transistors
94
and
95
is provided as a bias potential VBH to gates of P-channel MOS transistors of internal circuits
82
and
83
, and a constant current Ic flows through internal circuits
82
and
83
. Moreover, a gate potential of N-channel MOS transistors
96
and
97
is provided as a bias potential VBL to gates of N-channel MOS transistors of internal circuits
84
and
85
, and constant current Ic flows through internal circuits
84
and
85
.
A reference potential generating circuit
100
as shown in
FIG. 15
, for example, is provided to an internal circuit
83
. Reference potential generating circuit
100
includes P-channel MOS transistors
101
to
104
connected in series between an external power-supply potential extVdd line and a ground potential GND line. P-channel MOS transistor
101
is equal in size to P-channel MOS transistor
94
. The gate of P-channel MOS transistor
101
receives bias potential VBH generated by constant-current source circuit
81
. Gates of P-channel MOS transistors
102
and
103
are both connected to the drain of P-channel MOS transistor
103
. The gate of P-channel MOS transistor
104
is grounded. The drain of P-channel MOS transistor
101
becomes an output node N
101
.
P-channel MOS transistors
102
and
103
each operate as a resistance element. P-channel MOS transistor
104
is large enough for Ic and operates as a diode. P-channel MOS transistor
101
and P-channel MOS transistor
94
of constant-current source circuit
81
form a current mirror circuit so that constant current Ic flows through P-channel MOS transistors
101
to
104
of reference potential generating circuit
100
. If the total resistance value of P-channel MOS transistors
102
and
103
is R
102
, and the threshold voltage of P-channel MOS transistor
104
is Vt
104
, a reference potential VR=Ic×R
102
+Vt
104
would be output from output node N
101
.
Here, Ic×R
102
takes on the positive temperature characteristic of Ic, while the temperature characteristic of Vt
104
is negative. By setting the positive temperature characteristic of Ic×R
102
and the negative temperature characteristic of Vt
104
to balance out, the temperature characteristic of reference potential VR can be cancelled. Otherwise, either one of resistance value component Ic×R
102
and threshold component Vt
104
can be made dominant so that reference potential VR indicates either the positive or the negative temperature characteristic.
Reference potential VR is used as a reference when generating various internal potentials, such as an internal power-supply potential intVdd that is lower than an external power-supply potential extVdd, and a boosted potential Vpp for transmitting the exact high data level by keeping the resistance value of an N-channel MOS transistor in its conductive state sufficiently small.
Internal circuit
84
is provided with a Vbb level detection circuit
110
as the one shown in
FIG. 16
, for example. Vbb level detection circuit
110
includes P-channel MOS transistors
111
,
112
, N-channel MOS transistors
113
to
117
, fuses
118
to
120
, and a comparator
121
. MOS transistors
111
,
113
to
116
are connected in series between an external power-supply potential extVdd line and a substrate potential Vbb line. MOS transistors
112
,
117
are connected in series between an external power-supply potential extVdd line and a ground potential GND line.
Gates of P-channel MOS transistors
111
,
112
are both connected to the drain (node N
111
) of P-channel MOS transistor
111
. P-channel MOS transistors
111
and
112
form a current mirror circuit. Gates of N-channel MOS transistors
113
,
117
receive bias potential VBL generated in constant-current source circuit
81
. Gates of N-channel MOS transistors
114
to
116
are all grounded. Fuses
118
to
120
are connected in parallel to N-channel MOS transistors
114
to
116
, respectively.
Comparator
121
compares the potential of node N
111
with the potential of a node N
112
to output a

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