Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-06
2002-04-16
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S307000, C257S308000, C257S309000, C438S253000, C438S396000, C438S398000
Reexamination Certificate
active
06373084
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor memory storage devices, and more particularly to the design of capacitor electrodes for use in integrated circuits.
BACKGROUND OF THE INVENTION
Capacitors are used in a wide variety of semiconductor circuits. Because capacitors are of special importance in dynamic random access memory (DRAM) circuits, the invention will therefore be discussed in connection with DRAM circuits. However, the invention has broader applicability to any other memory circuits in which capacitors are used.
DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.
FIG. 1
illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells
10
. For each cell, the capacitor
14
has two connections, located on opposite sides of the capacitor
14
. The first connection is to a reference voltage, which is typically one half of the internal operating voltage (the voltage corresponding to a logical “1” signal) of the circuit. The second connection is to the drain of the FET
12
. The gate of the FET
12
is connected to the word line
18
, and the source of the FET is connected to the bit line
16
. This connection enables the word line
18
to control access to the capacitor
14
by allowing or preventing a signal (a logic “0” or a logic “1”) on the bit line
16
to be written to or read from the capacitor
14
.
The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and three contacts: one each to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and to increase memory cell density to allow more memory to be squeezed onto a single memory chip.
Because the capacitor in a memory cell usually occupies a large portion of the cell area, many efforts at achieving higher cell packing density focus on reducing the semiconductor area occupied by the capacitor. Maintaining or increasing capacitance of a capacitor as its relative area is decreased is necessary not only to maintain charge at the refresh rates used, but also to facilitate information detection and decrease soft errors resulting from alpha particles.
In order to minimize the area occupied by a capacitor and maximize capacitance, various storage cell designs have been developed, including planar capacitors, stacked capacitor (STC) cells, and trench capacitors. Planar capacitors are located next to the transistor, stacked capacitors are stacked or placed over the access transistor, and trench capacitors are formed in the wafer substrate beneath the transistor. Most large capacity DRAMs use stacked capacitors because of their greater capacitance, reliability, and ease of formation.
One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube having an oval or cylindrical shape when viewed from the top down. The wall of the tube consists of two plates of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon) separated by a dielectric. The bottom end of the tube is closed. The outer wall is in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open (the tube is filled with an insulative material later in the fabrication process). The sidewall and closed end of the tube form a container, hence the name “container capacitor.”
In addition, methods of forming a rough surface on the storage electrode of a capacitor have been developed to increase the capacitance by increasing the surface area of the storage electrode. One of the most successful techniques for creating a rough surface is the formation of hemispherical-grain (HSG) polysilicon nodules on the surface of the storage electrode.
As memory cell density continues to increase, efficient use of space becomes ever more important. Therefore, what is needed is a capacitor that maximizes surface area without increasing the proportion of cell area occupied by the capacitor relative to the other cell components.
SUMMARY OF THE INVENTION
The present invention provides an improved storage electrode for a container capacitor formed to span more than one cell in length. The narrow, elongated capacitor has a larger perimeter, resulting in increased capacitor wall area and therefore increased capacitance over the typical capacitor, without increasing the amount of cell area occupied by the capacitor. Methods for forming the improved storage electrode capacitor are also disclosed.
Advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.
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M. Sakao et al., A Capacitor-Over-Bit-line (COB) Cell With a Hemispherical-Grain Storage Node for 64 Mb DRAMs, pp. 27.3.1-27.3.4., IEDM, 1990.
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Dickstein , Shapiro, Morin & Oshinsky, LLP
Lebentritt Michael S.
Wilson Christian D.
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