Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-13
2002-04-23
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S587000, C438S597000, C438S682000
Reexamination Certificate
active
06376373
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which a silicide layer is formed, for example, on a source/drain diffusion layer or the like of a MOS (metal oxide semiconductor) transistor.
2. Description of the Related Art
As semiconductor integrated circuit pattern become finer, it is required to develop a transistor forming technology called a salicide structure with which both the gate electrode and the source/drain diffusion layer of a MOS transistor can be made low-resistance electrodes. For example, a Co salicide structure is formed by a directional sputtering of Co such as “long-throw sputtering” in which a metal film is formed with a distance between the metal material target and the semiconductor substrate (refer, for example, to
Ulvac Technical Journal
Vol. 47 (1997), p.35). By applying this directional sputtering to the manufacture of a CMOS logic device, a Co film with comparatively excellent coverage can be deposited even in a narrow diffusion layer region between gate electrodes and at the same time, Co of substantially the same thickness can be deposited both in a wide region and in a narrow region, so that a low-resistance Co silicide layer having the same sheet resistance in both of the regions can be formed.
A conventional case where a Co film is deposited by directional sputtering will be described with reference to
FIGS. 2A and 2B
. As shown in
FIG. 2A
, source/drain diffusion layers
3
isolated by device isolating portions
2
are present on an Si substrate
1
, and between the diffusion layers
3
, polysilicon gate electrodes
5
,
6
,
7
and
8
with a height of 0.2 &mgr;m are formed, with gate oxide films
4
in between, so as to be sandwiched by side walls
9
comprising insulating films. In this example, the distance between the gate electrodes
5
and
6
is, for example, 1.0 &mgr;m, and the distance between the gate electrodes
7
and
8
is 0.5 &mgr;m. On this structure, a Co film
10
with a thickness of 10 nm is deposited by directional sputtering (FIG.
2
B). In this directional sputtering, Co atoms from a Co target bombarded by Ar plasma are made substantially vertically incident on the Si substrate
1
so as to be deposited thereon, and as shown in
FIG. 2B
, a Co film
10
is formed that is approximately 9 nm thick in a central part A of a narrow region sandwiched by the gate electrodes
7
and
8
, and approximately 8 nm thick in a peripheral part B of the narrow region.
FIG. 2B
shows only a part in the vicinity of the polysilicon gate electrode
7
and
8
.
By performing a heat treatment in a postprocess, the Co film
10
deposited by this directional sputtering is caused to react with the Si substrate
1
, thereby forming a Co silicide layer on the Si substrate
1
. The silicide layer has a substantially uniform thickness irrespective of the distance between the gate electrodes as long as the distance is approximately 0.5 &mgr;m. Thus, a silicide layer having a uniform sheet resistance at least within the chip can be formed.
However, when the distance between the polysilicon gate electrodes
7
and
8
is reduced to approximately 0.2 &mgr;m, the region between the gate electrodes
7
and
8
is approximately 0.2 &mgr;m in depth and approximately 0.2 &mgr;m in width, so that the aspect ratio increases. Consequently, according to the above-described conventional method, even if the Co film is deposited by directional sputtering with 10 nm as the target thickness, the deposited Co film is only approximately 6 nm thick even at the thickest portion in the central part, whereas in the part where the distance between the gate electrodes is large, the Co film
10
is deposited substantially to the target thickness 10 nm. When the Co film is transformed into a silicide film by heat-treating such a specimen, a silicide layer is formed in which the thickness and the sheet resistance largely differ between the part where the distance between the polysilicon gate electrodes is large and the part where the distance is small (that is, the wide region and the narrow region) according to the difference in the thickness of the deposited Co film.
When such a Co silicide layer in which the thickness and the sheet resistance largely differ is formed, in etching to form a contact hole in an interlayer dielectric film formed on the Co silicide layer in the postprocess, a bottom of the contact hole passes through the Co silicide layer to reach the diffusion layer situated therebelow because of overetching in the part where the distance between the polysilicon gate electrodes is small. Consequently, the contact resistance increases. In addition, the operation speed varies among local circuits on a chip due to difference in diffusion layer resistance between the part where the distance between the polysilicon gate electrodes is large and the part where the distance is small. As described above, because of the increase in contact resistance in the part where the distance between the polysilicon gate electrodes is small and the variation in operation speed among local circuits, finished semiconductor devices become faulty, which deteriorates the manufacturing yield.
Moreover, increasing the thickness of the deposited Co film in the part where the distance between the polysilicon gate electrodes is small to the target thickness increases the thickness of the deposited Co film in the part where the distance between the polysilicon gate electrodes is large to be larger than the target thickness, so that the thickness of the CoSi
2
film formed in the part increases to increase the p-n junction leakage current in this part. Consequently, finished semiconductor devices become faulty, which deteriorates the manufacturing yield.
To improve the coverage of Co film in the part where the distance between the gate electrodes is small, it is considered to deposit Co by the CVD (chemical-vapor deposition) method. However, no industrial CVD method for depositing Co is present at the moment.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of manufacturing a semiconductor device, with which a silicide layer having the same thickness and sheet resistance as in the wide region with excellent metal coverage can be formed in the fine region having inferior coverage when the conventional manufacturing method is applied.
A method of manufacturing a semiconductor device of the present invention comprises the steps of: forming an oxide film on a semiconductor substrate; depositing a metal on the oxide film, and forming a reaction layer resulting from a reaction of the metal with a surficial portion of the semiconductor substrate through the oxide film; and removing the residual metal which has not reacted and the oxide film and then, transforming the reaction layer into a silicide layer by a high-temperature heat treatment.
According to the present invention, the oxide film is formed on the semiconductor substrate and the metal is deposited thereon, and the presence of the oxide film curbs the speed of reaction between the metal and the semiconductor substrate, so that a reaction layer of the same thickness as that in the wide region with excellent metal coverage can be formed in the fine region with inferior coverage. As a result, a silicide layer having the same thickness and sheet resistance in the fine region and in the wide region can be formed. By the substrate heating condition or the like in the metal deposition, not only the thickness of the reaction layer can be controlled but also the thickness of the silicide layer can be controlled.
Moreover, by forming a plurality of gate electrodes on a semiconductor substrate with a gate insulating film in between, forming a source/drain diffusion layer on a surface of the semiconductor substrate which surface is sandwiched between the gate electrodes, and forming an oxide film, a reaction layer and a silicide layer on the source/drain diffusion layer, a silicide layer of the same thickness and sheet resista
Nakamura Kikuko
Ogawa Shin-ichi
Sugiyama Tatsuo
Bowers Charles
Huynh Yennhu B.
Matsushita Electronics Corporation
Stevens Davis Miller & Mosher LLP
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