Method of locally forming metal silicide layers

Details Method of locally forming metal silicide layers Method of locally forming metal silicide layers

2001-11-30

2002-11-19

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S592000, C438S588000, C438S655000

Reexamination Certificate

active

06482738

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention generally relates to a method of locally forming metal silicide layers, and in particular to a method of locally forming metal silicide layers and avoiding a leakage current between memory cells caused by unwanted metal suicides.
2. Description of the Prior Art
In order to reduce the resistance and improve the performance of a integral circuit, a metal silicide layer, such as titanium silicide, is usually deposited on the surface of the circuit and elements. But in some regions where the resistance have to be kept high, such as the spaced region between two neighboring memory cells on the same word line, the metal silicide layer should be avoided. A conventional method is shown in FIG.
1
: first, a silicon substrate
100
is provided. There are at least two regions on the substrate
100
: one is an array region
101
, the other is a periphery region
102
. In the array region
101
, a dielectric layer
105
, such as an oxide-nitride-oxide (ONO) layer, is deposited on the substrate
100
. A memory array with gates
100
and sidewalls
130
is formed on the dielectric layer
105
, wherein a first spaced region
106
is existed between two neighboring memory cells on the same word line. In the periphery region
102
, there are at least a plurality of gates
120
of transistors and the sidewalls
140
of the gates
120
, wherein a second spaced region
107
is existed between two neighboring transistors. After a process of forming metal silicide, the metal silicide layers (
150
,
160
,
170
) are formed on the surface of the top of the gates
110
of memory cells, the surface of the top of the gates
120
of transistors, and the surface of silicon substrate
100
.
However, in the prior method the process of forming the sidewall
130
of the gates
100
of the memory cells is hard to control, so an overetching phenomenon frequently occurs to expose a part of the substrate
100
within the first spaced region
206
, as shown in FIG.
2
A. Thus a metal silicide layer
240
is also formed on the surface of silicon substrate
100
within the first spaced region
206
when the process of forming metal silicide is carried out. As shown in
FIG. 2B
, the metal silicide layer
240
on the surface of silicon substrate
100
within the first spaced region
206
will cause the leakage current, and degrade the performance of the memory cells.
SUMMARY
It is an object of the invention to provide a method of locally forming metal silicide layers on a integral circuit.
It is another object of the invention to provide a method to avoid a leakage current caused by the formation of metal silicide layers between memory cells on the same word line.
According to the foregoing objects, the present invention provides a method comprising the following steps: first, a silicon substrate is provided. The silicon substrate can be divided into at least two regions: one is the array region, the other is the periphery region. In the array region, an ONO layer is deposited on the substrate, and a plurality of first transistors, such as a memory array, is formed on the ONO layer. A first spaced region is existed between any two neighboring transistors of the plurality of the first transistors. In the periphery region, a plurality of second transistors are formed on the substrate, and a second spaced region is existed between any two neighboring transistors of the plurality of the second transistors. The second spaced region is larger than the first spaced region. Afterward, a first dielectric layer is conformally deposited to cover the surface of the substrate, the array region, the plurality of the first transistors, the periphery region, and the plurality of the second transistors. Then, an second dielectric layer is deposited on the first dielectric layer, wherein the thickness of those second dielectric layer within the first spaced region is larger than that of the second dielectric layer in any other region. A selective etching process is then performed to remove a partial second dielectric layer so that a part of first dielectric layer on the plurality of the first transistors is exposed. A part of the remaining second dielectric layer is within the first spaced region. A photoresist layer is then formed to cover the remaining second dielectric layer and the first dielectric layer. The part of the photoresist layer within the periphery region is then removed. By using the remaining photoresist layer as a mask, another etching process is performed to completely remove those second dielectric layer within the periphery region. Afterward, the remaining photoresist layer is also removed. Then, another selective etching process is performed to remove a partial first dielectric layer to form the sidewalls of the plurality of first transistors and the plurality of second transistors. At the same time, the top surface of the gates of the plurality of the first transistors and the plurality of the second transistors is exposed, and a part of the substrate within the periphery region is also exposed. Most of the first dielectric layer within the first spaced region remains, because a part of the second dielectric layer is existed within the first spaced region of array region. Afterward, a metal layer is deposited to cover the silicon substrate, the array region and the periphery region. A heating process is then executed to form metal silicide. Finally, the metal layer is removed.


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