Trench MOSFET with structure having low gate charge

Details Trench MOSFET with structure having low gate charge Trench MOSFET with structure having low gate charge

2000-08-31

2002-10-29

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000, C257S773000, C257S907000, C257S908000

Reexamination Certificate

active

06472708

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to microelectronic circuits, and more particularly to trench MOSFET devices.
BACKGROUND OF THE INVENTION
Metal oxide semiconductor field effect transistor (MOSFET) devices that use trench gates provide low turn-on resistance. In such trench MOSFET devices, the channels are arranged in a vertical manner, instead of horizontally as in most planar configurations.
FIG. 1
shows a partial cross-sectional view of a conventional trenched gate MOSFET device
2
. The MOSFET device includes a trench
4
filled with conductive material
6
separated from the silicon regions
8
by a thin layer of insulating material
10
. A body region
12
is diffused in an epitaxial layer
18
, and a source region
14
is in turn diffused in the body region
12
. Due to the use of these two diffusion steps, a transistor of this type is frequently referred to as a double-diffused metal oxide semiconductor field effect transistor with trench gating or, in brief, a “trench DMOS”.
As arranged, the conductive and insulating materials
6
and
10
in the trench
4
form the gate
15
and gate oxide layer
16
, respectively, of the trench DMOS. In addition, the depth L measured from the source
14
to the epitaxial layer
18
constitutes the channel length L of the trench DMOS device. The epitaxial layer
18
is a part of the drain
20
of the trench DMOS device.
When a potential difference is applied across the body
12
and the gate
15
, charges are capacitively induced within the body region
12
adjacent to the gate oxide layer
16
, resulting in the formation of the channel
21
of the trench DMOS device. When another potential difference is applied across the source
14
and the drain
20
, a current flows from the source
14
to the drain
20
through the channel
21
, and the trench DMOS device is said to be in the power-on state.
Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,907,776, 5,072,266, 5,541,425, and 5,866,931, the entire disclosures of which are hereby incorporated by reference.
A typical discrete trench MOSFET circuit includes two or more individual trench MOSFET transistor cells which are fabricated in parallel. The individual trench MOSFET transistor cells share a common drain contact, while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete trench MOSFET circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor.
Unit cell configurations of trench MOSFET circuits can take various forms.
FIGS. 2A and 2B
illustrate two trench configurations commonly employed in the prior art. In contrast to
FIG. 1
, which represents a partial cross-sectional side (or elevation) view of a single trench section within a MOSFET circuit,
FIGS. 2A and 2B
represent partial overhead (or plan) views of two trench networks. In particular,
FIG. 2A
illustrates a partial section of a trench network
4
in which the trenches collectively form a series of hexagonal unit cells (an expanded view would show the cells to be in a honeycomb pattern).
FIG. 2B
illustrates a partial section of a trench network
4
in which the trenches form a series of square unit cells (an expanded view would show the cells to be arranged in the fashion of squares in a grid).
FIG. 2B
can be thought of as being formed by the intersection of two sets of parallel trench lines. All trench areas (i.e., all dark regions) of
FIGS. 2A and 2B
are of essentially the same depth within the trench network.
Demand persists for trench DMOS devices having ever-lower on-resistance. The simplest way to reduce on-resistance is to increase cell density. Unfortunately, the gate charges associated with trench DMOS devices increase when cell density is increased.
Hence, efforts to provide low on-resistance in trench DMOS devices by increasing cell density are presently frustrated by detrimental changes that simultaneously occur, for example, in the gate charges associated with those devices.
SUMMARY OF THE INVENTION
The above and other obstacles in the prior art are addressed by the trench MOSFET devices and methods of the present invention.
According to an embodiment of the invention, a trench MOSFET device is provided. The trench MOSFET device comprises:
a) a semiconductor substrate of first conductivity type;
b) an epitaxial region of first conductivity type provided within a lower portion of a semiconductor epitaxial layer disposed on the substrate, wherein the epitaxial region of first conductivity type has a lower majority carrier concentration than the substrate;
c) a region of second conductivity type provided within an upper portion of the semiconductor epitaxial layer;
d) a plurality of trench segments in an upper surface of the semiconductor epitaxial layer, wherein: i) the plurality of trench segments extend through the region of second conductivity type and into the epitaxial region of first conductivity type, ii) each trench segment is at least partially separated from an adjacent trench segment by a terminating region of the semiconductor epitaxial layer, and iii) the trench segments define a plurality of polygonal body regions within the region of second conductivity type;
e) a first insulating layer at least partially lining each trench segment;
f) a plurality of first conductive regions within the trench segments adjacent to the first insulating layer, wherein each of the first conductive regions is connected to an adjacent first conductive region by a connecting conductive region that bridges at least one of the terminating regions; and
g) a plurality of source regions of the first conductivity type positioned within upper portions of the polygonal body regions and adjacent the trench segments.
The body regions are preferably either rectangular body regions defined by four trench segments or hexagonal body regions defined by six trench segments.
In some preferred embodiments: i) the trench MOSFET device is a silicon device, ii) the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity, and more preferably the substrate is an N+ substrate, the epitaxial region of first conductivity type is an N region, the body regions comprise P regions, and the source regions are N+ regions, iii) the first insulating layers are oxide layers, iv) the first conductive regions and the connecting conductive regions are polysilicon regions and/or v) a drain electrode is disposed on a surface of the substrate and a source electrode is disposed on at least a portion of the source regions.
According to another embodiment of the invention, a method of forming a trench MOSFET device is provided. The method comprises:
a) providing semiconductor substrate of first conductivity type;
b) forming a semiconductor epitaxial layer over the semiconductor substrate, the epitaxial layer being of the first conductivity type and having a lower majority carrier concentration than the substrate;
c) forming a region of second conductivity type within an upper portion of the semiconductor epitaxial layer (for example, by a method comprising implanting and diffusing a dopant into the epitaxial layer), such that an epitaxial region of first conductivity type remains within a lower portion the semiconductor epitaxial layer;
d) forming a plurality of trench segments in an upper surface of the epitaxial layer (for example, by a method comprising forming a patterned masking layer over the epitaxial layer and etching the trenches through the masking layer), wherein: (i) the trench segments extend through the region of second conductivity type and into the epitaxial region of first conductivity type, (ii) each trench segment is at least partially separated from an adjacent trench segment by a terminating region of the semiconductor epitaxial layer, and (iii) the trench segments define a plurality of polygonal body regions within the region of second conductivity type;
e) forming a first insulating layer within each

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