Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-08
2002-10-22
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S393000, C257S903000
Reexamination Certificate
active
06469356
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor memory devices such as SRAMs (static random access memories).
2. Description of Related Art
SRAMs, one type of semiconductor memory devices, do not require a refreshing operation, and therefore have characteristics that can simplify a system in which they are incorporated and facilitate lower power consumption. For this reason, the SRAMs are prevailingly used as memories for hand-carry type equipment, such as cellular phones.
It is preferable for the hand-carry type equipment to be reduced in size. Therefore, the memory size of the SRAMs must be reduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device that can reduce the size of memory cells.
In accordance with the present invention, a semiconductor memory device has a memory cell including a first driver transistor, a second driver transistor, a first load transistor, a second load transistor, a first transfer transistor and a second transfer transistor. The semiconductor device includes a first gate electrode layer and a second gate electrode layer. The first gate electrode layer includes gate electrodes of the first driver transistor and the first load transistor. The second gate electrode layer includes gate electrodes of the second driver transistor and the second load transistor. The first gate electrode layer and the second gate electrode layer have linear patterns, respectively, and are disposed in parallel with each other. Distances between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located and on the side where the driver transistors are located are different from each other.
In accordance with the present invention, distances between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located and on the side where the driver transistors are located are different from each other. Accordingly, in accordance with the present invention, the memory cell region can be effectively utilized. As a result, while the memory cell can be further reduced in size, its characteristics are enhanced such that its power consumption is lowered and its operation is more stabilized. For example, the memory cell region can be effectively utilized in the following manner. The distance between the first gate electrode layer and the second gate electrode layer on the side where the driver transistors are located may be set such that a source contact layer of the driver transistors (where the source contact layer is a conduction layer that is used to connect a source region and a wiring layer) can be disposed inside a gate electrode interlayer region (where the gate electrode interlayer region is a region between the first gate electrode layer and the second gate electrode layer), and the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located may be set to a minimum value on the design rule.
In accordance with the present invention, the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located (for example, 0.2-0.4 &mgr;m) may be set to be shorter than the distance between the first gate electrode layer and the second gate electrode layer on the side where the driver transistors are located (for example, 0.41-0.6 &mgr;m). The first embodiment of the invention described above includes the feature that distances between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located and on the side where the driver transistors are located are different from each other. In accordance with a second embodiment of the invention, the distance between the first gate electrode layer and the second gate electrode layer on the side where the driver transistors are located (for example, 0.2-0.4 &mgr;m) may be shorter than the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located (for example, 0.41-0.6 &mgr;m).
The first embodiment may be preferable in the present invention. In an SRAM memory, a current that reads the cells on the order of 100 &mgr;A flows through the driver transistors. Therefore, a parasitic resistance in the source regions of the driver transistors needs to be lowered. On the other hand, while the load transistors that function to maintain a cell node high potential side can have a smaller current capacity, an off-leak current needs to be reduced. In accordance with the first embodiment, the distance between the first gate electrode layer and the second gate electrode layer is shorter on the side where the load transistors are located than on the side where the driver transistors are located. Also, the source contact layer on the side of the driver transistors is disposed in the gate electrode interlayer region, and the source contact layer on the side of the load transistors is disposed outside to avoid the gate electrode interlayer region. Therefore, the parasitic resistance at the source sections of the driver transistors can be reduced, such that a higher and more stable operation can be realized. Also, a channel section and an area on the drain-side of the load transistor can be provided with wide regions because the distance between the first gate electrode layer and the second gate electrode layer is short. As a result, the channel length of the load transistor can be made longer than that of the driver transistor. Accordingly, the leak current resulting from the short-channel effect of the load transistor can be reduced. As a result, in accordance with the first embodiment of the present invention, the memory cell region can be effectively utilized, with the result that, while the characteristics are enhanced for lower current consumption and more stable operation, the memory cell can be further miniaturized.
In accordance with the present invention, a source contact layer for the load transistors is located adjacent to end sections of the first and second gate electrode layers on the side of the load transistors. The end sections bend outwardly to avoid contact with the source contact layer for the load transistors. In accordance with the present invention, by outwardly bending the end sections, an area of the gate electrode layer on the outside of the channel region of the load transistors (the source contact side of the load transistors) can be made large. Accordingly, even when there is an alignment error, the gate electrode layer can cover the channel region of the load transistor, whereby an increase in the channel leak current of the load transistors can be prevented. Also, in accordance with the present invention, since the end sections are outwardly bent, the shape of the end sections corrects the light proximity effect. As a result, in accordance with the present embodiment, a proximity effect correction device, such as shelves does not need to be added to the end sections.
In accordance with the present invention, the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located is a minimum value on the design rule.
When the distance between the first gate electrode layer and the second gate electrode layer on the side where the load transistors are located is a minimum value on the design rule, the source resistance of the load transistors increases. However, since the load transistor has a small current capacity, its characteristics do not deteriorate. Therefore, in accordance with the present invention, the memory cell can be reduced in size without sacrificing its characteristics.
In accordance with the present invention, load transistors are p-channel type. Generally, p-channel type transistors have a greater short-channel effect (that leads to an increased punch-through curre
Kodaira Satoru
Kumagai Takashi
Noda Takafumi
Takeuchi Masahiro
Chaudhuri Olik
Oliff & Berridg,e PLC
Pham Hoai
Seiko Epson Corporation
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