Method and structure for creating high density buried...

Details Method and structure for creating high density buried... Method and structure for creating high density buried...

2001-03-16

2002-08-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S151000, C438S155000, C438S249000

Reexamination Certificate

active

06436744

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The Technical field of the invention is that of semiconductors, in particular silicon-on-insulator (SOI) structures.
2. Related Art
A cell circuit schematic of a static random access memory (SPAM)
10
is shown in FIG.
1
A. NFETs T
1
and T
2
are two input-output (IO) devices connecting a bit line BL and a complementary bit line BLN to a cell latch
11
. The NFETs T
3
and T
4
, and the PFETs T
5
and T
6
, form the cell latch
11
. In bulk technology, all the NFETs T
1
-T
4
share a same grounded substrate or body. In silicon-on-insulator (SOI) technology, however, each NFET T
1
-T
4
has its own floating p-type body. The SOI PFETs T
5
and T
6
also have their own n-type bodies.
FIG. 1B
provides a plan view of the NFETs T
1
-T
4
of a physical structure that makes up the electrical circuit of the SRAM
10
represented in FIG.
1
A.
SRAM cell stability is reduced due to floating body effects when the SRAM cell is built on silicon-on-insulator (SOI) structures. There are two weaknesses inherent in the floating body. First, the capacitances from the various array nodes (bit-line, true, complement, etc.) to the device bodies swing the body voltages of the NFETs in the cell and transfer devices from voltages of −0.5V to Vdd (see
FIG. 1A
) above ground, depending on the history of use of the array. Second, minor defects resulting in leakages to NFET bodies, of the order of only micro amperes, can further mismatch body bias among the NFETs in the cell.
The mismatch within the cell can be aggravated by the floating bodies and needs to be lessened or eliminated to avoid a cell read error. The differences in the body voltages of the passgate NFETS contribute directly to the cell instability. The smaller the voltage difference during switching, the more reliable the data output will be.
A conventional bulk wafer FET
30
is shown in FIG.
1
C and includes a metal or semiconductor gate
31
on a gate dielectric
32
, such as silicon dioxide, which insulates the gate
31
from a silicon wafer
33
. A region under the gate dielectric
32
comprises a silicon body
34
formed by type dosing of the silicon wafer
33
.
FIG. 1C
shows the FET
30
as an NFET having p-type doping of the silicon wafer
33
. If the FET
30
were a PFET, the doping of the silicon wafer
33
would be n-type doping. The silicon body
34
acts as a source or sink for combination of electron/hole pairs during the FET
30
operation. A source
35
is provided under the gate
31
and on a first side of the gate
31
, and a drain
36
is provided under the gate
31
and on a second side of the gate
31
.
In operation of the conventional bulk wafer FET
30
, a voltage is applied to the source
35
or the drain
36
, depending upon whether the FET
30
is a NFET or a PFET. When no voltage is applied to the gate
31
, almost no current will flow between the source
35
and the drain
36
and the FET
30
is OFF. When a voltage is applied to the gate
31
, electrons or holes form an inversion channel in the body
34
underneath the gate
31
. This allows conduction between the source
35
and the drain
36
. Thus, a current flows from the source
35
to the drain
36
, and the device is ON. The boundaries of the source
35
and the drain
36
are not perfect, and current leaks to the body
34
in both the ON and OFF states. Since the body
34
is grounded to a ground
37
, there is a path to the ground
37
for excess holes or electrons to dissipate rapidly. While the conventional bulk wafer FET
30
does not suffer from floating body effects, the FET
30
does not benefit from advantages afforded by SOI structures.
In the operation of a SOI FET, the electrons or holes that leak from the source/drain to the body have no path by which to dissipate. Thus the charge gets stored in the body, which changes the body voltage and the threshold voltage of the device, making the cell unstable.
A method and structure is needed for avoiding floating body effects when SOI structures are used.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor structure, comprising:
a conductive substrate;
an insulating layer on the conductive substrate;
a semiconductor device layer on the insulating layer,
wherein the semiconductor device layer includes a semiconductor material;
a conductive buried body contact in conductive contact with the conductive substrate, wherein the buried body contact extends through the insulating layer and through less than a total thickness of the semiconductor device layer, and wherein the buried body contact conductively contacts a region of the semiconductor device layer, said region including the semiconductor material.
The present invention provides a method of forming and using a semiconductor structure, comprising the steps of:
providing a silicon-on-insulator structure having a conductive substrate, an insulating layer on the conductive substrate, and a semiconductor device layer on the insulating layer, wherein the semiconductor device layer includes a semiconductor material;
forming a first trough that extends through the semiconductor device layer and through the insulating layer; and
forming a conductive buried body contact in the first trough and in conductive contact with the conductive substrate, wherein the buried body contact extends through the insulating layer and through less than a total thickness of the semiconductor device layer to a height H above a top surface of the conductive substrate, and wherein the buried body contact conductively contacts a region of the semiconductor device layer, said region including the semiconductor material.
The present invention provides a method and structure which avoids floating body effects when SOI structures are used.
The present invention may be used with a SRAM circuit or other types of circuits using silicon-on-insulator (SOI) constructions.
The present invention reduces cell instability and obtains high performance logic and SRAMs in a high performance SOI semiconductor device.


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