Computer graphics processing and selective visual display system – Computer graphics display memory system – Plural storage devices
Reexamination Certificate
1999-06-14
2002-11-12
Chauhan, Ulka J. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Plural storage devices
C345S503000, C345S531000, C345S519000, C345S419000
Reexamination Certificate
active
06480199
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a graphic image processing apparatus, more specifically relates to the technical field of arrangement and interconnection of a built-in memory especially in the case where a DRAM or other memory and a logic circuit are provided together.
2. Description of the Related Art
Computer graphics are often used in a variety of CAD (computer aided design) systems and amusement machines. Especially, along with the recent advances in image processing techniques, systems using three-dimensional computer graphics are becoming rapidly widespread.
In three-dimensional computer graphics, the color value of each pixel is calculated at the time of deciding the color of each corresponding pixel. Then, rendering is performed for writing the calculated value to an address of a display buffer (frame buffer) corresponding to the pixel.
One of the rendering methods is polygon rendering. In this method, a three-dimensional model is expressed as a composite of triangular unit graphics (polygons). By drawing using the polygons as units, the colors of the pixels of the display screen are decided.
In polygon rendering, coordinates (x, y, z), color data (R, G, B), homogeneous coordinates (s, t) of texture data indicating a composite image pattern, and a value of the homogeneous term q for the respective vertexes of the triangle in a physical coordinate system are input and processing is performed for interpolating these values inside the triangle.
Here, coordinates in a UV coordinate system of an actual texture buffer, namely, texture coordinate data (u, v), are comprised of the homogeneous coordinates (s, t) divided by the homogeneous term q to give “s/q” and “t/q” which in turn are multiplied by texture sizes USIZE and VSIZE, respectively.
FIG. 11
is a view of the system configuration of the basic concept of a three-dimensional computer graphic system.
In the three-dimensional computer graphic system, data for drawing a graphic image is given from a main memory
2
of a main processor
1
or an I/O interface circuit
3
for receiving external graphic data to a rendering circuit
5
having a rendering processor
5
a
and a frame buffer
5
b
via a main bus
4
.
The rendering processor
5
a
is connected to a frame buffer
5
b
intended to hold data for display and a texture memory
6
for holding texture data to be applied on the surface of a graphic element to be drawn (for example, a triangle).
The rendering processor
5
a
is used to perform the processing for drawing a graphic element with a texture applied to its surface in the frame buffer
5
b
for every graphic element.
The frame buffer
5
b
and the texture memory
6
are generally composed by a dynamic random access memory (DRAM).
In the system shown in
FIG. 11
, the frame buffer
5
b
and the texture memory
6
are configured as physically separate memory systems.
Recently, it has become possible to provide a DRAM and a logic circuit together. Looking at graphic drawing image processing apparatuses, as shown in
FIG. 12
, there are ones attempting to build a DRAM or other large capacity memory
7
a
on the same semiconductor chip
7
as a drawing use logic circuit
7
b
while keeping the previous structure of use of an external memory as it is.
In this case, a DRAM core having an equivalent control mechanism as a general-purpose DRAM is simply arranged next to the prior graphic drawing image processing logic circuit and the two are interconnected by a single path.
There are only the above types in the case of graphic drawing image processing apparatuses.
Below, although the technical field is different from that of a graphic drawing image processing apparatus, the trends in the field of microprocessors will be described.
In the past, it has been proposed to provide a microprocessor and a memory on a single chip. Proposals have also been made regarding the arrangement of the memory on the chip.
For example, in a PPRAM (ISSCC97/SESSION14/Parallel Processing RAM), as shown in
FIG. 13
, DRAMs
8
a
-
1
to
8
a
-
4
serving as main memories and microprocessors (P)
8
b
-
1
to
8
b
-
4
are built in on the same semiconductor chip
8
.
Note that, in
FIG. 13
, reference numerals
8
c
-
1
to
8
c
-
4
indicate memory controllers (Mem CTL) of the DRAMs
8
a
-
1
to
8
a
-
4
, and
8
d
-
1
to
8
d
-
4
indicate caches.
In this semiconductor chip
8
, the DRAMs
8
a
-
1
to
8
a
-
4
serving as the main memories are arranged in only one direction with respect to the microprocessors
8
b
-
1
to
8
b
-
4
.
Also,
FIG. 13
shows a configuration wherein a plurality of microprocessors
8
b
-
1
to
8
b
-
4
access single DRAMs via the caches
8
d
-
1
to
8
d
-
4
.
Turning to the problems to be solved by the invention, in the above conventional so-called built-in DRAM system, however, when a frame buffer memory and a texture memory are separated into different memory systems, there is a disadvantage that the frame buffer emptied due to a change of the display resolution cannot be used for the texture. Alternatively, when the frame memory and the texture memory are physically combined, the overhead of the page exchange of the DRAM etc. becomes large at the time of simultaneous success of the frame memory and the texture memory, so there is a disadvantage that the performance has to be sacrificed.
Also, with a method of interconnection wherein a DRAM core having a control mechanism equivalent to a general-purpose DRAM is arranged next to a graphic image processing logic circuit and the two are connected by a single path, the bandwidth for accessing is not improved at all in spite of the trouble of building in the DRAM and becomes a bottleneck in system performance.
Furthermore, a built-in main memory type microprocessor has the following disadvantages:
Namely, the semiconductor chip
8
has four units of the same functional configuration aligned with each other and transfers data through the memory controllers. The bandwidths of the transfer are determined by the path widths of the memory controllers and the operating speeds. The fastest path is one cutting straight across the chip. The operating speed is determined by the longest path. Therefore, improvement of the operating speed becomes difficult. Long paths naturally occupy a greater area in the layout.
The trend has been for the speed of microprocessors to double every 18 months and for the memory capacity to also double about every 18 months.
In spite of this situation, the access time increases about 7% per year. How to make the access time faster is now becoming the key to improving the system performance.
In the above conventional method, the larger the chip, the longer the critical path and therefore the more the operating speed ends up being hampered.
Accordingly, the access time between DRAMs is left unimproved, so the merits of building in DRAMs do not appear that much.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an image processing apparatus capable of effectively utilizing a storage circuit provided together with a logic circuit and enabling an increase of the operating speed and reduction of the power consumption without causing a deterioration of performance.
According to a first aspect of the present invention, there is provided an image processing apparatus comprising a storage circuit divided into a plurality of storage modules, each storage module storing image data of different pixels and a logic circuit for performing predetermined processing on the image data based on the stored data of the storage circuit, the storage circuit and the logic circuit being both accommodated on one semiconductor chip, and the plurality of divided storage modules arranged at peripheral portions of the logic circuit.
According to a second aspect of the invention, there is provided an image processing apparatus for performing rendering by receiving polygon rendering data including three-dimensional coordinates (x, y, z), R (red), G (green), and B (blue) data, homogeneous coordinates (s, t
Kato Yu
Kita Katsuya
Oomori Mutsuhiro
Chauhan Ulka J.
Kananen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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