Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-02-02
2002-06-11
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000, C438S724000, C438S756000, C438S757000
Reexamination Certificate
active
06403492
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
Reference is made to commonly-assigned, concurrent-filed application Ser. No. 09/773,231, entitled “Method of Manufacturing Semiconductor Devices with Trench Isolation”, which is herein incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method of manufacturing semiconductor devices which include trench isolation.
2. Description of the Related Art
Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds, and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices include a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically includes source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor.
A typical method of trench formation includes initially growing a pad oxide layer on the substrate, and depositing a nitride polish stop layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material (or “trench fill”), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP) using the nitride layer as a polish stop, and the nitride and pad oxide are stripped off the active areas to complete the trench isolation structure.
One problem with prior trench isolation methods is that use of the polish stop and the pad oxide creates a topological step in the resulting device. Such a topological step may make it difficult, for example, to photolithographically process subsequent layers of the device with accuracy, particularly in forming submicron features, thereby adversely affecting process yield and production cost. In addition, such a topological step may adversely affect the uniformity of thickness of subsequently formed layers of material.
SUMMARY OF THE INVENTION
A method of trench isolation includes removal of insulation material after planarization of the insulation material and before stripping of a nitride layer such as polish stop layer. The removal of insulation material may be accomplished, for example, by etching. The amount of material removed may be selected so that a surface of the device is substantially planar after one or more subsequent processing steps.
According to an aspect of the invention, a method of trench isolation includes polishing deposited insulation material used to fill trenches, to the level of a polish stop, removing a further amount of the insulation material, and stripping the polish stop.
According to another aspect of the invention, a method of trench isolation includes multiple etchings of insulation material used to fill trenches, one of the etchings occuring before stripping an imbedded nitride element, and another of the etchings occuring after stripping of the nitride element.
According to yet another aspect of the invention, a method of trench isolation includes compensating for the height of polish step elements by removing insulation material below the level of a upper surface of the polish stop elements prior to removing the polish stop elements.
According to still another aspect of the invention, a method of forming a semiconductor device on a substrate includes the steps of: forming a pad oxide layer on the substrate; forming a polish stop layer on the pad oxide layer; selectively removing portions of the polish stop layer, the pad oxide layer, and underlying portions of the substrate, thereby forming trenches in the polish stop layer and leaving polish stop elements of the polish stop layer; depositing an insulating material to fill the trenches; planarizing the insulating material; performing a first etch of the insulating material; removing the polish stop elements; and performing a second etch of the insulating material.
According to a further aspect of the invention, a method of forming a semiconductor device with a planar surface includes the steps of: planarizing a surface of insulating trench fill material by removing insulating material until the trench fill material is substantially flush with top surfaces of polish stop elements within the insulating materials; performing a first etch of the trench fill material; removing the polish stop elements; and performing a second etch of the trench fill material.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
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Buynoski Matthew S.
Chan Darin A.
Renner , Otto, Boisselle & Sklar, LLP
Tran Binh X.
Utech Benjamin L.
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