Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-16
2002-04-23
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S393000
Reexamination Certificate
active
06376884
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor apparatus. More particularly, the present invention relates to a CMOS type SRAM having a dummy cell outside a cell array.
2. Description of the Related Art
The typical configurations of a memory cell array and its periphery in a typical semiconductor memory will be described below. The semiconductor memory is usually provided with a plurality of memory cell arrays and a plurality of peripheral circuits. In the memory cell array, memory cells for storing information are arrayed continuously in lines and rows. The peripheral circuit is composed of a sense amplifier, an address decoder, a circuit for driving them, and the like.
The memory cell array occupies most of a chip area in the semiconductor memory. Thus, in order to reduce the chip area, the memory cell is highly integrated under a minutely dimensional accuracy close to a minimum machining dimension in a manufacturing process. The optical continuation of a mask pattern used to form the memory cell array is lost in a boundary between the memory cell array and the peripheral circuit.
For this reason, when the mask pattern is viewed from the inside of the memory cell array, it is shifted from a dense mask pattern to a rough mask pattern, in the boundary. Thus, an exposure strength received by a resist is different depending on a difference between the roughness and the density. This leads to a difference between patterns formed from the resist pattern. For example, gate electrodes, source and drain diffusion layers, and connection hole diameters of MOS transistors are respectively manufactured in different dimensions between the inside of the memory cell array and the end of the memory cell array adjacent to the boundary of the peripheral circuit.
The reason of the variation in the exposure and diffusion condition is described in further detail. The respective patterns of the memory cell at the end in the memory cell array are complex and minute. However, there is no minute pattern in the peripheral circuit adjacent to the end of the memory cell array, as compared with the memory cell. Thus, in the peripheral circuit adjacent to the end of the memory cell array, regularities, such as detour, reflection and the like, with regard to light in the resist exposure are different from those within the memory cell array. Because of this difference, a resist film can not be exposed accurately in accordance with the pattern. Hence, in an extreme case, a defect caused by a pattern break is induced in the memory cell at the end of the memory cell array. This results in a drop of a yield of a chip.
Typically, one or more dummy cells, each of which has the same shape as the memory cell and does not carry out a storing operation, are placed at the end of the memory cell array, in order to avoid the above-mentioned problems. Thus, the suppression of the pattern break in the memory cell for carrying out the storing operation can protect the drop of the yield.
With regard to the semiconductor apparatus targeted for the present invention in which the memory cell array is composed of a CMOS type memory cell, their problems will be described below.
A p-type transistor is formed in a region of an n-well to which a positive power supply potential is sent. An n-type transistor is formed in a region of a p-well to which a ground potential is sent. A diffusion layer for sending a potential to a well in a memory cell is positioned in a boundary of a peripheral circuit outside the dummy cell at the end of the memory cell array. The positive power supply potential is sent through an n-type diffusion layer to the n-well, and the ground potential is sent through a p-type diffusion layer to the p-well.
FIG. 1
shows a plan view of a diffusion layer structure at the above-mentioned conventional end of the memory cell array.
60
denotes a memory cell array. CMOS transistors
48
are regularly arrayed in the memory cell array
60
.
61
denotes a peripheral circuit, and
62
denotes a dummy cell region.
53
denotes a diffusion layer region for sending potentials to wells respectively. An n-type diffusion layer
44
is formed in an n-well
42
as the diffusion layer for sending the potential to the well. A p-type diffusion layer
46
is formed in a p-well
51
as the diffusion layer for sending the potential to the well.
A p-type diffusion layer
43
is formed in the dummy cell region
62
and the memory cell array
60
in the n-well region
42
. An n-type diffusion layer
45
is formed in the dummy cell region
62
and the memory cell array
60
in the p-well region
51
.
FIG. 2
shows a sectional view of a portion denoted by a straight line Z-Z′ crossing the dummy cell region
62
and the memory cell array
60
in the n-well region
42
in
FIG. 1. 41
denotes a p-type semiconductor substrate, and it is usually fixed to the ground potential.
In the semiconductor memory, the memory cell array is usually divided because of the limitation of a pre-charge current in a digit line for inputting and outputting a data stored in a memory cell and the delay of a word signal line for selecting memory cells. The peripheral circuits, such as a decoder for controlling the word signal line and the like, are mounted between the divided memory cell arrays.
In the conventional semiconductor memory circuit, a diffusion layer for sending a potential to a well and a dummy cell are mounted in a boundary between a memory cell array and a peripheral circuit. Thus, an area necessary for the boundary between the memory cell array and the peripheral circuit is increased proportionally to the division of the memory cell array. This results in the increase of the area of the semiconductor memory circuit.
Japanese Laid Open Patent Application (JP-A-Heisei, 5-226615) discloses the following semiconductor memory. Accumulation nodes constituting a dummy cell array are integrally connected to each other. Then, a drive potential Vcc is sent to them. Also, a diffusion layer for forming a drain of a selection transistor is connected by using a conductive layer for forming a bit line. Then, the drive potential Vcc is sent to it. Thus, the potential Vcc is sent to an N-type diffusion layer constituting a source and a drain of the selection transistor.
Japanese Laid Open Patent Application (JP-A-Heisei, 10-84087) discloses the following semiconductor memory circuit. Typically, sense amplifiers and memory cells are alternately mounted in a center of a memory array. At both ends of the memory array, an N-well region is positioned on a side of a boundary between the memory array and a periphery, and an end sense amplifier at which a p-well region is located is mounted within it. Then, a Deep N-well region is formed in a lower layer of the N-well region and the P-well region in the memory array. Its end extends up to a middle of the lower layer of the P-well region in the periphery. Also, a sub contact region, a well contact region and a sub contact region are arranged in order starting from outside a chip.
SUMMARY OF THE INVENTION
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor apparatus, which is constituted in a minimum cell array area, while a cell array property is maintained in which a dummy cell is used.
In order to achieve an aspect of the present invention, a semiconductor apparatus, includes: a cell having a first conductivity type of diffusion layer formed in a second conductivity type of semiconductor region, wherein the second conductivity type is opposite to the first conductivity type; and a dummy cell having the second conductivity type of dummy diffusion layer formed in the semiconductor region, wherein the dummy cell is adjacent to the cell.
In order to achieve another aspect of the present invention, a semiconductor memory apparatus, includes: a memory cell having a first conductivity type of memory diffusion layer formed in a second conductivity type of semiconductor
Chaudhuri Olik
Pham Hoai
LandOfFree
Semiconductor apparatus, which is constituted in minimum... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor apparatus, which is constituted in minimum..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor apparatus, which is constituted in minimum... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2919305