Method for in-line testing of flip-chip semiconductor...

Details Method for in-line testing of flip-chip semiconductor... Method for in-line testing of flip-chip semiconductor...

2000-08-25

2002-04-09

Karlsen, Ernest (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06369602

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates in general to semiconductor manufacturing and, more specifically, to in-line testing of flip-chip semiconductor assemblies.
2. State of the Art
As shown in
FIG. 1
, in a conventional process
10
for manufacturing flip-chip semiconductor assemblies, singulated dice are flip-chip attached with a conductive epoxy or solder to a printed circuit board (PCB) or other substrate to form a flip-chip semiconductor assembly. Once the dice are attached by curing of the epoxy or reflow of the solder, the dice are then encapsulated, underfilled, or both, using a non-conductive epoxy or other encapsulation material. The electrical characteristics of the flip-chip semiconductor assembly are then tested and, if the assembly passes the test, it is selected for shipping to customers.
If the flip-chip semiconductor assembly does not pass the test, then it proceeds to a repair station, where it is repaired using one or more known-good dice (KGD)
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(i.e., dice that have already passed all standard electrical tests and have been through burn-in). Specifically, those dice in the assembly that are believed to have caused the assembly to fail the test are electrically disconnected from the rest of the assembly, typically using laser fuses. One or more KGD are then attached to the PCB of the assembly to replace the disconnected dice. Once the KGD are attached, the assembly is retested and, if it passes, it too is selected for shipping to customers.
The conventional KGD repair process described above generally works well to repair flip-chip semiconductor assemblies, but the process necessary to produce KGD can be an expensive one. Also, the described KGD repair process does not test for, or repair, problems with the interconnections between the dice and the PCB in a flip-chip semiconductor assembly. Rather, it only repairs problems with non-functioning dice or defective solder bumps. Finally, the KGD in the described repair process end up going through burn-in twice: a first time so they can be categorized as a KGD, and a second time when the flip-chip semiconductor assembly to which they are attached goes through burn-in. This is obviously a waste of burn-in resources and also stresses the KGD far beyond that necessary to weed out infant mortalities.
Therefore, there is a need in the art for a method of testing flip-chip semiconductor assemblies that reduces or eliminates the need for the KGD repair process described above.
BRIEF SUMMARY OF THE INVENTION
In a method for electrically testing a flip-chip semiconductor assembly in .accordance with this invention, the assembly is tested using, for example, an in-line or in-situ test socket or probes, after one or more integrated circuit (IC) dice and a substrate, such as a printed circuit board (PCB), are brought together to form the assembly, and before the IC dice are encapsulated or otherwise sealed for permanent operation. As a result, any problems with the IC dice or their interconnection to the substrate can be fixed before sealing of the dice complicates repairs. The method thus avoids the problems associated with conventional known-good-die (KGD) repairs. Also, speed grading can be performed while the dice are tested.
The assembly may be manufactured using a “wet” conductive epoxy, such as a heat-snap-curable, moisture curable, or radiation curable epoxy, in which case bond pads on the IC dice can be brought into contact with conductive bumps on the substrate formed of the epoxy for the testing, which can then be followed by curing of the epoxy to form permanent die-to-substrate interconnects if the assembly passes the test. If the assembly does not pass the test, the lack of curing allows for easy repair. After curing but before sealing of the IC dice, the assembly can be tested again to detect any interconnection problems between the IC dice and the substrate.
The assembly may also be manufactured using a “dry” conductive epoxy, such as a thermoplastic epoxy, for conductive die-attach, in which case the IC dice and the substrate can be brought together and the epoxy cured to form permanent die-to-substrate interconnections, after which the testing may take place. Since the testing occurs before sealing of the IC dice, repair is still relatively easy.


REFERENCES:
patent: 4677528 (1987-06-01), Miniet
patent: 5315241 (1994-05-01), Ewers
patent: 5483174 (1996-01-01), Hembree et al.
patent: 5528157 (1996-06-01), Newberry et al.
patent: 5641996 (1997-06-01), Omoya et al.
patent: 5798652 (1998-08-01), Taraci

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