Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-23
2002-04-09
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S306000, C257S315000, C257S368000, C257S390000
Reexamination Certificate
active
06369416
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, more particularly to a method and system for reducing charge gain and charge loss due to contacts in semiconductor devices, such as a flash memory device.
BACKGROUND OF THE INVENTION
A conventional semiconductor device, such as a memory, includes a large number of cells, which are typically floating gate devices such as floating gate transistors. For example,
FIG. 1
depicts a portion of a conventional semiconductor device
10
. The semiconductor device
10
includes cells
20
,
30
, and
40
formed on a substrate
11
. Each cell includes a gate stack
21
,
31
and
41
. Each gate stack
21
,
31
and
41
includes a floating gate
22
,
32
and
42
, respectively, and a control gate
24
,
34
and
44
, respectively. The cells
20
,
30
and
40
also include drains
29
and
39
and sources
19
and
49
. As depicted in
FIG. 1
, the cells
20
and
40
share a common drain
29
, while the cells
20
and
30
share a common source
19
. Typically, each cell
20
,
30
and
40
also includes spacers
26
and
28
,
36
and
38
, and
46
and
48
, respectively.
In order to make electrical contact to one or more of the cells
20
,
30
and
40
, a conventional electrical contact
52
is provided. The conventional contact
52
is provided within a conventional contact hole
50
. The conventional contact hole
50
is provided in an insulating layer
54
which otherwise covers the cells
20
,
30
and
40
. The insulating layer
54
insulates the cells
20
,
30
and
40
. The conventional contact hole
50
is filled with a conductive material to form the conventional contact
52
.
Although the conventional semiconductor device
10
functions, one of ordinary skill in the art will readily realize that the conventional semiconductor device
10
is subject to unanticipated charge gain and charge loss because of the spacing of the contact
52
from a particular cell, such as the cell
20
. The current trend in semiconductor technology is toward higher densities. In order to reduce the space occupied by a given conventional semiconductor device
10
, the components of the semiconductor device are more densely packed and made smaller. Thus, the cells
20
,
30
and
40
and the conventional contact
52
are relatively close. The thickness of the spacers
26
and
28
,
36
and
38
and
46
and
48
is between approximately one thousand and two thousand Angstroms. The conventional contact
52
is approximately 0.2 to 0.4 &mgr;m wide. This distance is approximately the smallest that an aperture in a photoresist mask (not shown) can be made. The photoresist mask is used to form the conventional contact hole
50
. The sides of the conventional contact hole
50
and, therefore, the sides of the conventional contact
52
are also almost perpendicular to the surface of the substrate
11
. For example, the conventional contact hole
50
is typically formed so that the edges make an angle, &bgr;, of greater than eighty-eight degrees. Thus, the top of the contact
52
is approximately directly above the bottom of the contact
52
. The conventional contact
52
is also closely spaced to neighboring cells
20
,
30
and
40
. In particular, the distance between the base of the conventional contact
52
and the edge of a nearest gate in a gate stack, such as the gate stack
21
, is very small.
The small spacing between the conventional contact
52
and the gate stack of a particular cell, such as the cell
20
, causes unanticipated charge gain and charge loss from the cell
20
. Because the conventional contact
52
is typically separated from the edge of the gate stack
21
by such a small distance, the portion of the insulating layer
54
between the conventional contact
52
and the gate stack
21
is very thin. The combination of the spacer
28
and the insulating layer
54
may not provide sufficient insulation to prevent the gate stack
32
from being electrically coupled to the conventional contact
52
through the spacer
28
and insulating layer
54
. For example, charge on the conventional contact
52
may travel to the gate stack
21
when a user does not desire the floating gate
22
to store charge. Similarly, a charge stored on the floating gate
22
may travel to the conventional contact
52
. Thus, a charge intentionally stored on the floating gate
22
may bleed away. Consequently, the cell
20
is subject to unanticipated charge gain and charge loss. As a result, the cell
20
may not function as desired.
Accordingly, what is needed is a system and method for providing contacts in a semiconductor device which has reduced charge gain and charge loss. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and system for providing a contact in a semiconductor device including a plurality of gates. The method and system comprise providing an insulating layer substantially surrounding at least a portion of the plurality of gates and providing at least one contact in the insulating layer. The at least one contact has a side defining a sloped profile. The sloped profile includes an angle between the side of the contact and a surface of the substrate that is less than approximately eighty-eight degrees.
According to the system and method disclosed herein, the present invention provides a greater spacing between the contact and the closest gate stack without increasing the spacing between gate stacks or between the center of the contact and the gate stack. Consequently, a higher density of devices can be achieved while reducing the charge gain and charge loss through the contact.
REFERENCES:
patent: 5739563 (1998-04-01), Kawakubo et al.
patent: 6171970 (2001-01-01), Xing et al.
patent: 6177351 (2001-01-01), Beratan et al.
patent: 07297297 (1995-11-01), None
Hui Angela T.
Pham Tuan Duc
Ramsbey Mark T.
Sun Yu
Advanced Micro Devices , Inc.
Flynn Nathan
Forde Remmon R.
Sawyer Law Group LLP
LandOfFree
Semiconductor device with contacts having a sloped profile does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with contacts having a sloped profile, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with contacts having a sloped profile will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2917025