Method for fabricating borderless and self-aligned...

Details Method for fabricating borderless and self-aligned... Method for fabricating borderless and self-aligned...

2000-10-26

2002-11-05

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S763000, C257S767000, C438S597000, C438S598000, C438S618000

Reexamination Certificate

active

06476488

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to integrated circuit semiconductor devices, and more particularly to a method for fabricating multilevel interconnections having self-aligned and borderless polysilicon and metal landing plug contacts for integrated circuits. The method is particularly useful for making polysilicon N doped landing plugs for low current leakage to N
−
contacts on the substrate, while concurrently making metal contacts to N
+
and P
+
contacts on the substrate for low contact resistance.
(2) Description of the Prior Art
Ultra Large Scale Integrated (ULSI) circuits fabricated on semiconductor substrates require multilevels of metal interconnections to electrically interconnect the discrete semiconductor devices on the semiconductor chips. In the conventional method, the different levels of metal interconnections are separated by layers of insulating material. These interposed insulating layers have etched contact holes and via holes which are used to electrically connect the metal layers to the underlying semiconductor substrate and to other underlying patterned conducting layers, such as doped polysilicon, polycide (polysilicon/silicide) layers, and the like.
However, in future generations of integrated circuits, as the minimum feature sizes of semiconductor devices decrease (for example, minimum feature sizes of 0.25 um or less) the lines/spacings shrink. This results in aspect ratios (height/width) of the contact holes or via holes increasing dramatically. Therefore, the contact openings to different underlying N
−
, N
+
, and P
+
contacts on the substrate and to tungsten silicide and/or tungsten lines are difficult to make because of the contact opening high aspect ratio. This makes it difficult to etch reliable contact holes to the substrate without damaging the substrate.
To better appreciate this problem,
FIG. 1
shows a schematic cross-sectional view of a partially completed integrated circuit on a semiconductor substrate having the conventional contact openings by the prior art. The cross section shows a substrate
10
having field effect transistors (FETs) with gate electrodes
16
with a cap oxide
18
and sidewall spacers
20
, and a gate oxide
14
. Lightly doped source/drain areas
17
(N
−
) are formed adjacent to the gate electrodes on some of the FETs in device areas of a first type, for low current leakage contacts, while N
+
and P
+
contacts
19
(N
+
or P
+
) are formed in device areas of a second type for low contact resistance (Rc), such as for CMOS circuits. A planar first insulating layer or an inter-polysilicon oxide (IPO) layer
20
is used to insulate the FETs and on which the next level of electrically conducting lines
24
, such as tungsten silicide or tungsten, are formed having a cap oxide layer
26
and sidewall spacers
28
. A second insulating layer
40
is deposited to insulate the electrically conducting lines
24
, and is planarized. Electrical connections are then made by etching high-aspect-ratio contact openings C to the substrate
10
, to the FET gate electrodes
16
, and to the next level of inter-connections
24
. When these contacts are etched to the shallow N
−
contacts on the substrate, it is difficult to avoid overetching (notching) of the substrate and destroying the N
−
, N
+
, and P
+
contact-to-substrate junctions, as depicted by the points N in FIG.
1
. Also, for these closely spaced gate electrodes
16
, it is difficult to etch the contact C to the substrate without etching into the polysilicon gate electrode, resulting in electrical shorts as depicted by the point S in FIG.
1
. Also, in etching contacts C to the substrate, it is difficult to avoid overetching the contacts C′ to the next level of inter-connecting lines
24
, as depicted by the point O in FIG.
1
.
Several methods of making high-aspect-ratio borderless contacts are reported in the literature. One method for making borderless contacts is described in U.S. Pat. No. 4,966,870 to Barber et al., in which a silicon nitride etch-stop layer is used on the substrate when the borderless contact is etched in an overlying silicon oxide layer. Other methods for making high-aspect-ratio borderless contacts in insulators are described by Liang et al., U.S. Pat. No. 5,665,623, in which borderless contacts are made to source/drain areas that are less than the minimum feature size of the current photolithographic resolution utilizing the lateral oxidation resulting from the field oxide when the local oxidation of silicon (LOCOS) is used. Huang et al., U.S. Pat. Nos. 5,674,781 and 5,654,589, describe a method and structure in which a titanium/titanium nitride (Ti/TiN) layer is used to make a Ti/TiN stacked interconnect structure to form local inter-connects and contact landing pads on the same level.
Therefore there is still a need in the industry to provide a simpler method for making improved landing plugs for multilevel interconnect structures, which reduces the aspect ratios of contact openings and prevents substrate damage.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to make polysilicon and metal contact landing plugs with self-aligned borderless contacts for multilevel interconnections on integrated circuits.
It is another object of the present invention to concurrently make metal/polysilicon interconnecting lines during formation of the polysilicon/metal contact landing plugs, thereby simplifying the manufacturing process steps.
Still another object of this invention is to form N
+
polysilicon contacts to N
−
doped substrate contacts, and concurrently to form metal contacts to N
+
and P
+
doped regions to provide improved (low) contact resistance (Rc).
It is another object of this invention to utilize the polysilicon and metal contact landing plugs to etch contact openings with reduced aspect ratio.
Yet another objective of this invention is to use the process for making these polysilicon/metal plug landing contacts to make improved dynamic random access memory (DRAM) circuits.
This invention describes a method for making polysilicon and metal landing plugs as borderless and self-aligned contacts for multilevel interconnections. The method provides a means for forming N
+
doped polysilicon plugs to N
−
doped substrate contacts for low leakage currents, as is typically desired for capacitor node contacts on DRAM device, while providing metal contacts to N
+
and P
+
doped contacts on the substrate for low contact resistance (Rc), such as in the peripheral areas of the DRAM chips for CMOS circuits.
The method begins by providing a semiconductor substrate having first and second device areas wherein the first device areas require N
+
polysilicon contacts to N
−
substrate contacts, while the second device areas require metal contacts to the heavily doped N
+
and P
+
contacts on the substrate. Typically the substrate is a single-crystal silicon having a <
100
> crystallographic orientation and includes N and P wells for making P-channel and N-channel FETs having these P
+
and N
+
contacts, respectively. A relatively thick Field OXide (FOX) is formed that surrounds and electrically isolates the device areas in and on the substrate. One conventional method of forming the field oxide areas is by shallow trench isolation (STI), as commonly practiced in the industry. The FETs are formed next by growing a thin gate oxide by thermal oxidation on the device areas. An N
+
doped polysilicon layer and a refractory metal silicide layer are deposited to form a polycide layer. A cap oxide composed of silicon oxide/silicon nitride is deposited on the polycide layer, and the multilayer is then patterned to form the gate electrodes having this cap oxide. Lightly doped source/drain (LDD) areas are implanted adjacent to the gate electrodes to improve the device characteristics (minimize short-channel effects). Borde

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