Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-17
2002-06-04
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S306000, C257S307000, C257S310000, C257S311000, C257S532000
Reexamination Certificate
active
06399974
ABSTRACT:
BACKGROUND OF THE ION
1. Field of the Invention
The present invention relates generally to a semiconductor dev ice and a method for manufacturing the same. More specifically, the i nvention relates to a stacked semiconductor memory device using a ferr oelectric or a high-dielectric (high-&egr; material (&egr;: permittivity)) film for a capacitor of a memory cell, and a method for manufacturing t he same.
2. Description of the Prior Art
FIG. 9
is a sectional view of a structure of a memory cell of a conventional stacked semiconductor memory device using a ferroelectric or high-dielectric film for a capacitor.
In the surface part of a silicon substrate
1
, an element isolating film
2
for isolating element regions is formed every one memory cell, and three gate diffusion layers
4
are formed at regular intervals every one memory cell. On each of portions serving as channel regions between adjacent two of the gate diffusion layers
4
of the silicon substrate
1
, a gate
3
of each of MOS transistors is formed so that the end portion of the gate
3
overlaps with the gate diffusion layers
4
arranged on both sides. A first interlayer insulator film
5
is formed on the silicon substrate
1
, on which the gates
3
have been formed. A first contact holes
6
′ is formed in the first interlayer insulator film
5
above each of the gate diffusion layers
4
. In each of the first contact holes
6
′, a first contact interconnection layer
6
is formed.
For each memory cell, a second interconnection layer
8
is connected to one of the three gate diffusion layers
4
, which is commonly used for two of the MOS transistors, via one of the first contact interconnection layers
6
, and a first interconnection layer
7
is connected to each of two of the gate diffusion layers
4
, each of which is dedicated for a corresponding one of two of the MOS transistors, via one of the first contact interconnection layers
6
. A second interlayer insulator film
9
is formed on the first interlayer insulator film
5
, on which the first interconnection layer
7
and the second interconnection layer
8
have been formed. On the second interlayer insulator film
9
, there are formed capacitors, each of which has a capacitor bottom electrode
10
, a capacitor insulator film
11
and a capacitor top electrode
12
, so that each of the capacitors corresponds to each of two of the three gate diffusion layers
4
, each of which is dedicated for a corresponding one of two of the MOS transistors.
A third interlayer insulator film
13
is formed on the second interlayer insulator film
9
, on which the capacitors have been formed. In order to connect the third interconnection layer
7
to the capacitor top electrode
12
, a second contact hole
14
′ is formed in portion of the second interlayer insulator film
9
and the third interlayer insulator film
13
above each of the first interconnection layers
7
, and a third contact hole
15
is formed in a portion of the third interlayer insulator film
13
above each of the capacitors. A second contact interconnection layer
14
is formed in each of the second contact holes
14
′, and a third contact interconnection layer
15
is formed in the third contact hole
15
′. A third interconnection layer
16
of a multilayer interconnection layer is formed on the third interlayer insulator film
13
for connecting the first interconnection layer
7
to the capacitor top electrode
12
via the second contact interconnection layer
14
and the third contact interconnection layer
15
. Moreover, an interconnection protecting insulator film
17
is formed on the whole surface of the third interlayer insulator film
13
, on which the third interconnection layer
16
has been formed.
The above-described stacked semiconductor memory device functions as a non-volatile memory, such as an EPROM and an EEPROM, when the capacitor insulator film
11
between the capacitor bottom electrode
10
and the capacitor top electrode
12
is formed of a ferromagnetic having a spontaneous dielectric polarization while no electric field is applied, and functions as a volatile memory, such as a DRAM, when the capacitor insulator film
11
is formed of a high-dielectric having a high dielectric.
FIGS. 10 through 12
are sectional views showing a process for manufacturing the memory cell of the conventional stacked semiconductor memory device shown in FIG.
9
.
The memory cell of the conventional stacked semiconductor memory device of
FIG. 9
is produced by a following manufacturing method.
First, as shown in
FIG. 10
, an element isolating film
2
for isolating regions is formed every one memory cell in the surface part of a silicon substrate
1
by a thermal oxidation and a photolithography so as to have a thickness of, e.g., about 5000 angstroms(1 angstrom=10 nm). Thereafter, for each one memory cell, a gate oxide film
3
a
of a gate
3
of a MOS transistor is formed on the silicon substrate
1
by the thermal oxidation so as to have a thickness of, e.g., about 100 angstroms. In addition, a tungsten silicide layer serving as a gate interconnection layer
3
b
of the gate
3
is deposited on the gate oxide film
3
a
by a CVD method so as to have a thickness of, e.g., about 2000 angstroms. Moreover, a silicon nitride film serving as a gate protecting film
3
c
of the gate
3
is deposited on the gate interconnection layer
3
b
by the CVD method so as to have a thickness of, e.g., about 1000 angstroms. After the gate oxide film
3
a
, the gate interconnection layer
3
b
and the gate protecting layer
3
c
are formed, two gates
3
of MOS transistors are formed every one memory cell by the photolithography and an anisotropic etching (e.g., RIE). After the gates
3
are formed, three gate diffusion layers
4
serving as sources and drains of the MOS transistors are formed every one memory cell by an ion implantation and a thermal diffusion.
Then, as shown in
FIG. 11
, a first interlayer insulator film
5
is deposited by the CVD method so as to have a thickness of, e.g., about 6000 angstroms. In a portion of the first interlayer insulator film
5
above each of the gate diffusion layers
4
, i.e., in a portion for allowing a first contact interconnection layer
6
to be formed, a first contact hole
6
′ is formed by the photolithography and the RIE. After the first contact hole
6
′, a tungsten layer having a thickness of, e.g., about 4000 angstroms, is deposited by the CVD method so as to be embedded in the first contact hole
6
′, and etched to the surface of the first contact hole
6
′ by a isotropic etching (e.g., CDE) to form the first contact interconnection layer
6
. After the first contact interconnection layer
6
is formed, a tungsten layer is deposited by the CVD method so as to have a thickness of, e.g., about 4000. Then, for each memory cell, a second interconnection layer
8
, which is connected to the first contact interconnection layer
6
on one of three gate diffusion layers
4
commonly used for two of the MOS transistors, and a first interconnection layer
7
, which is connected to the first contact interconnection layer
6
on each of two of the gate diffusion layers
4
dedicated for two of the MOS transistors, respectively, are formed by the photolithography and the RIE.
After the first interconnection layer
7
and the second interconnection layer
8
are formed, a second interlayer insulator film
9
is deposited by the CVD method so as to have a thickness of, e.g., about 3000 angstroms, on the first interlayer insulator film
5
, on which the first interconnection layer
7
and the second interconnection layer
8
have been formed, as shown in FIG.
9
. After the second interlayer insulator film
9
is deposited, a platinum (Pt) film serving as a capacitor bottom electrode
10
of a capacitor is deposited by a sputtering method so as to have a thickness of, e.g., about 2000 angstroms, and a PZT (lead (Pb) zirconate titanate) film serving as a capacitor insulator film
11
of the capacitor is depos
Hogan & Hartson L.L.P.
Kabushiki Kaisha Toshiba
Lee Eddie
Warren Matthew E.
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