Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-07-06
2002-04-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C438S108000
Reexamination Certificate
active
06376917
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a plurality of semiconductor chips mounted on a substrate, and particularly to a semiconductor device suitable for realizing the reduction in size and weight of electronic equipment and the improvement of performances of the electronic equipment.
Recently, to reduce sizes of semiconductor chips and increase the level of integration of the semiconductor chips, a technology of mixedly mounting a at logic circuit, an analog circuit, and memories such as a DRAM and a flash memory on the same silicon substrate has been proposed and partially put into practical use.
The technology of mixedly mounting semiconductor chips on the same silicon substrate, however, has various technical problems caused by evolution of a process of fabricating each of the semiconductor chips.
For example, a thermal process necessary for forming a DRAM capacitor causes a problem in impairing an ultra-shallow junction profile essential for realizing a finer structure of a transistor in a logic chip, and also causes a problem in allowing boron in a gate electrode of a P-channel transistor to pass through a gate insulating film, to make a channel profile of the P-channel transistor different from a design profile, thereby degrading the current characteristics of the transistor.
An analog circuit, which interfaces with external chips such as a driver, an amplifier and sensor, requires a higher withstand voltage and a higher input range than those of an advanced CMOS, and accordingly, the analog circuit is hard to be made finer in its geometrical structure. For a semiconductor chip in which the above analog circuit is integrated with a logic LSI required to be made very finer in its geometrical structure, most of the semiconductor chip is occupied by the analog circuit hard to be reduced in its area, to reduce an economical merit obtained by mixed mounting of the analog circuit and the logic circuit.
In addition to the above technology of mixedly mounting semiconductor chips on the same silicon substrate, a technology of mixedly mounting semiconductor chips on a package level has been also positively promoted.
A so-called chip-on-chip structure including semiconductor chips simply stacked to each other is advantageous in shortening lengths of interconnections; however, it is disadvantageous in sacrificing reinforcement of power source lines and ground lines in the chips. In an ultra-high speed CPU or DSP, an excessive current flowing in a chip reduces an effective inner voltage due to resistances of a power supply line and a ground line, to thereby reduce the operational speed.
Even for a low power chip desired to realize operation at a significantly low supply voltage, the performance thereof may be significantly degraded by a slight reduction in potential due to resistances of interconnections. In particular, a chip desired to be operated at a voltage being as significantly low as 1 V or less, for example, a chip having a structure using an SOI (Si on insulator) substrate requires a very stable power supply line and a very stable ground line.
Against such a background, power supply lines and ground lines of chips have been conventionally formed from multi-level interconnections, and in recent years, a technology of forming bonding pads corresponding to a plurality of power supply lines and ground lines in chips and connecting them to interconnections formed in a substrate, thereby further stabilizing the power supply lines and ground lines of the chips has been put in practical use.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of mixedly mounting a logic chip, an analog chip, a memory chip, etc. by stacking them to each other while stabilizing power supply lines and ground lines of the chips.
To achieve the above object, according to the present invention, there is provided a semiconductor device including: an intermediate substrate having a conductive portion and also having, on its one surface, an external connection terminal conducted to the conductive portion; and semiconductor chips each having connection portions, the semiconductor chips being mounted on both the surfaces of the intermediate substrate; wherein at least two of the semiconductor chips are electrically conducted to each other via the conductive portion of the intermediate substrate; and at least one of a power supply line, a ground line, and a signal line of each of the semiconductor chips is connected to the conductive portion of the intermediate substrate via two or more, conducted to each other, of the connection portions.
With this configuration, since semiconductor chips such as a logic chip, an analog chip, a memory chip, etc. are mounted on both the surfaces of the intermediate substrate, it is possible to realize the mixed mounting of the semiconductor chips, and since at least one of the power supply line, ground line and signal line of each of the semiconductor chips thus mounted is connected to the conductive portion of the intermediate substrate via two or more, conducted to each other, of the connection portions, it is possible to stabilize the power supply lines, ground lines and signal lines of the semiconductor chips.
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patent: 5477082 (1995-12-01), Bcukley, III et al.
patent: 5977640 (1999-11-01), Bertin et al.
patent: 6075287 (2000-06-01), Ingraham et al.
patent: 6133637 (2000-10-01), Hikita et al.
patent: 6150724 (2000-11-01), Wenzel et al.
Takeshita Kaneyoshi
Yanagida Toshiharu
Le Bau T
Nelms David
Sonnenschein Nath & Rosenthal
Sony Corporation
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