Methods and apparatuses for managing multiple direct memory...

Details Methods and apparatuses for managing multiple direct memory... Methods and apparatuses for managing multiple direct memory...

2000-10-03

2002-08-13

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C709S250000, C370S402000

Reexamination Certificate

active

06434645

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to the field of computer systems, and real time processing systems. The present invention is more particularly related to methods and apparatuses for managing multiple direct memory access channels.
Since the advent of the computer system, efforts have been focused on increasing its speed and capabilities. One thrust in the technology has been aimed in the direction of peripheral devices. Peripheral devices are capable of handling specific functions that were once commonly performed by the central processing unit (CPU), the heart of the computer system. Today, peripheral cards and devices handle many types of specific tasks, allowing the CPU to handle the management of the computer system. For example, peripheral cards exist for audio processing, video processing, digital signal processing, modem interface, network interface, 3-D graphics processing and many more.
Indirectly, the proliferation of peripheral devices used in a computer system has increased the CPU's management burden. Peripheral systems typically need access to memory located on the computer system, or main memory. Conventionally, the CPU has been burdened with the task of managing transfer of data during a peripheral devices' accesses to the main memory.
Direct memory access systems have helped to relieve burden on the CPU.
FIG. 1
is a block diagram of a computer system
2
utilizing a direct memory access system. Computer system
2
includes a CPU
10
, a main memory
12
, a bus controller
13
, a direct memory access (DMA) controller
15
, a bus
20
and peripheral devices
30
,
32
and
33
. In the illustrated computer system, the peripherals are an audio processing card
30
, a video processing card
32
and a digital signal processing card
33
.
In the computer system, DMA controller
15
manages accesses to main memory
12
by peripherals
30
,
32
and
33
. Initially, a software application is normally implemented on CPU
10
, which controls the operation of a particular peripheral device, commonly referred to as a driver. Typically, the driver would initially set up a peripheral device, for example audio processing card
30
.
Another application implemented on CPU
10
might then request a sound to be played. The driver may then retrieve a piece of audio data from an external memory source, such as a disk drive, and place it in main memory
12
. The driver, through CPU
10
, would typically inform DMA controller
15
of the size of the data transfer. DMA controller
15
normally establishes a single direct memory access connection between main memory
12
and audio processing card
30
via bus
20
via bus controller
13
.
Throughout the transfer of the audio data between main memory
12
and audio processing card
30
, DMA controller
15
manages the DMA channel while CPU
10
manages the transfer to data from the memory source to main memory
12
, as will be discussed further below. The constant interaction between CPU
10
, DMA controller
15
and main memory
12
adds to the duties of the CPU. Essentially, the peripheral devices are slaves and CPU
10
and DMA controller
15
are the masters, which means that the CPU and the DMA controller have the responsibilities of establishing and maintaining the data transfer through the DMA channels between main memory
12
and the peripheral devices
30
,
32
, and
33
.
Additionally, computer systems are typically capable of only establishing a limited number of DMA channels between main memory
12
and peripherals
30
,
32
and
33
. Typically, only one DMA channel is established per peripheral device. The limited number of DMA channels limits the number of peripheral devices that may be connected to bus
20
, and the amount of information that may be transferred from main memory
12
to the peripheral devices.
In more recent systems, computer systems have incorporated a peripheral component interconnect (PCI) bus and an associated controller to increase the bandwidth between main memory and peripheral devices, referring to FIG.
2
.
FIG. 2
depicts a prior art computer system
3
utilizing a peripheral component interconnect bus
21
. Computer system
3
typically includes CPU
10
, main memory
12
, a PCI bus controller
16
, PCI bus
21
, and PCI compatible peripheral devices
40
,
42
and
43
.
An advantage of PCI bus
21
is that it is capable of handling more data than older prior art buses, as well as allowing peripherals to act as bus masters. For example, current PCI buses are normally capable of handling 132-266 megabytes per second, and as high as 572 megabytes per second. Older prior art buses have typically been limited to about 33 megabytes per second (e.g., ISA buses are limited about 8.3 mbps and EISA buses are limited to 33 mbps).
Another difference between PCI bus
21
and older buses is the capability of establishing a greater number of DMA channels between main memory
12
and peripheral devices, partly because peripherals can act as bus masters. However, even the PCI computer system
3
typically only establishes one DMA channel per peripheral device between main memory
12
and a particular peripheral device
40
,
42
and
43
. Thus, while the bandwidth of a DMA channel established between main memory
12
and a peripheral device may be increased, up to the bandwidth of PCI bus
21
, the DMA channel is still limited to the bandwidth of the particular bus
21
.
Therefore, the introduction of a PCI bus into prior art computer systems, has only somewhat alleviated the bandwidth limitations of older prior art computer systems. Additionally, the PCI bus has only partially solved the management problems associated with DMA data transfers. In computer system
3
, the peripherals handle the transfer of data after a DMA channel has been initiated. Therefore, some of the responsibilities of establishing and maintaining a DMA channel have been relegated to peripheral devices
40
,
42
and
43
.
In a typical operation, a driver is implemented on CPU
10
, for example an audio processing peripheral driver. A request by another application for the playback of audio data normally triggers the driver, vis a vis CPU
10
, to move the requested audio data from an external source to main memory
12
. The driver informs audio peripheral
40
that the requested audio data is ready for retrieval. Audio processing peripheral
40
acts as the master rather than the PCI bus controller
16
and CPU
10
directing the actual transfer. Audio processing peripheral
40
typically sends a request to PCI bus controller
16
for access to PCI bus
21
. The other peripherals
42
and
43
may also be requesting control of the PCI bus, and PCI bus controller arbitrates the requests in order to allow the orderly transfer of information from main memory
12
to the various peripherals
40
,
42
and
43
.
In that respect, PCI bus controller
16
and CPU
10
are relieved of the duty of keeping track of and establishing DMA channels with the various peripherals. However, even in PCI based computer systems CPU
10
may be overly burdened with the management of the actual transfer of the data from main memory
12
to peripherals
40
,
42
and
43
.
Typical methods of managing data in main memory and the transfer of data to a peripheral vary, referring to
FIGS. 3-5
.
FIG. 3
depicts a memory map of main memory
12
of either
FIG. 1
or
FIG. 2. A
driver implemented on CPU
10
may retrieve a requested block of data
50
from another memory medium and store it in main memory
12
. As illustrated, data
50
may be segmented into multiple data segments
50
(
0
)-
50
(
n
). Data segments
50
(
0
)-
50
(
n
) also may be segmented in a non-sequential order.
Assuming the above situation of transferring data to audio processing peripheral
40
, in order to pass along data segments
50
(
0
)-
50
(
n
) to audio processing peripheral
40
, one method has been to utilize ping and pong buffers
55
and
56
, respectively. Generally, data segments
50
(
0
)-
50
(
n
) are copied from their respectiv

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