Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-15
2002-07-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S197000
Reexamination Certificate
active
06423992
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a manufacturing technique therefor; and, more particularly, the invention relates to a technique which is effective for application to a DRAM or a semiconductor integrated circuit device, wherein the DRAM and a logic circuit, such as a logical control circuit or an arithmetic logic circuit or the like, are placed on one semiconductor substrate in mixed form.
Memory cells of a DRAM are generally placed at points where a plurality of word lines and a plurality of bit lines intersect on a principal surface of a semiconductor substrate in matrix form. Each memory cell comprises one memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and one information storage capacitive element (capacitor) electrically connected in series therewith. The memory cell selection MISFET is formed within an active region whose periphery is surrounded by a device separation region, and principally comprises a gate oxide film, a gate electrode constructed integrally with each word line, and a pair of semiconductor regions constituting a source and a drain. Each bit line is placed in an upper portion of the memory cell selection MISFET and is electrically connected to one of the source and drain shared between two adjacent memory cell selection MISFETs in an extending direction thereof The information storage capacitive element is similarly placed in the upper portion of the memory cell selection MISFET and is electrically connected to the other of the source and drain.
A DRAM described in Japanese Patent Application Laid-Open No. Hei 7-7084 has been devised to provide a lower electrode (storage electrode) of each capacitor in a cylindrical form having an opening defined thereabove thereby to increase its surface area. Further, a capacitive insulating film is formed on the lower electrode and an upper electrode (plate electrode) is formed over the capacitive insulating film.
In a capacitor having such a lower electrode of cylindrical shape, a steplike offset or difference in level corresponding to the height of the capacitor occurs between a memory cell array region and a region other than a peripheral circuit region or the like.
If such a steplike offset exists, it is then difficult to adjust the exposure focus upon patterning an interconnection layer formed after the formation of the capacitor. As a result, fine wiring patterns cannot be obtained. With developments in miniaturization of a semiconductor integrated circuit device, the storage capacitive value required per unit area has increased and, therefore, the height of the capacitor has further increased. On the other hand, allowable margin values for adjustment of the exposure focus become increasingly more strict due to the miniaturization of each wiring pattern.
Japanese Patent Application Laid-Open No. Hei 4-10651 (corresponding U.S. Pat. No. 5,218,219) discloses a DRAM wherein in order to reduce the steplike offset between the aforementioned memory cell array region and peripheral circuit region, grooves are defined in an insulating film and capacitors are formed along inner walls of the grooves.
SUMMARY OF THE INVENTION
In the aforementioned DRAM, however, an insulating film having a thickness equal to the height of each capacitor is left within a region other than the memory cell array region. In the micro-fabricated DRAM, there may be cases in which the thickness of the insulating film reaches 1 &mgr;m in terms of the need for increasing the height of the capacitor to ensure its storage capacity. Therefore, when a first layer interconnection formed before a capacitor forming process is connected to a second layer interconnection formed after the formation of the capacitor, it is necessary to define each connecting-hole in the thick insulating film having a thickness equal to the height of the capacitor, so that the aspect ratio (corresponding to the depth of the connecting hole relative to the open diameter of the connecting hole) of the connecting hole increases. Namely, even if the first layer interconnection and the second layer interconnection are connected to one another by a plug, they are inevitably connected to one another by a plug, having a high aspect ratio. Thus, the yield might be reduced because a plug having such a high aspect ratio is formed. Further, the connecting hole reaches a substrate in an etching process for the formation of the connecting hole, so that the second layer interconnection and the substrate are short-circuited.
In a semiconductor integrated circuit device in which a DRAM and a logic circuit, such as a logical control circuit or a logic circuit or the like, are placed on a single semiconductor substrate in mixed form, the logic circuit part has a configuration in which a first layer interconnection and a second layer interconnection are connected by a plug having a high aspect ratio in a manner similar to a peripheral circuit of the DRAM. If the interconnections are connected by the plug having such a high aspect ratio, then the resistance thereof interferes with the performance, such as a quick response or the like of the logic circuit.
Incidentally, Japanese Patent Application Laid-Open No. Hei 9-92794 discloses a method of simultaneously forming capacitor-forming concave portions and plug-forming grooves in an insulating film to reduce a steplike offset and simplify a process for processing storage electrodes. However, the disclosed method has a problem in that, when an interconnection (second layer interconnection) is formed after the formation of each capacitor, a CMP method cannot be used. When a lower electrode of the capacitor is formed simultaneously with the second layer interconnection of a peripheral circuit according to the features described in this publication, a capacitive insulating film of the capacitor is formed after a process for forming the second layer interconnection. When the capacitive insulating film is composed of an oxide metal, such as a tantalum oxide or the like, in order to obtain an increase in the stored charge of the capacitor, it is necessary inevitably to perform a heat treating process at a high temperature. A metal material, such as low-resistance copper or aluminum or the like, used for the second layer interconnection cannot be adopted from the viewpoint of thermal diffusibility and softening.
An object of the present invention is to improve the reliability of connection between a first layer interconnection and a second layer interconnection placed with a thick insulating film having a thickness equal to the height of each capacitor interposed therebetween in a semiconductor integrated circuit device having memory cells containing capacitive elements.
Another object of the present invention is to reduce the resistance of a hole portion for connection between the first layer interconnection and the second layer interconnection.
A further object of the present invention is to reduce the resistance of interconnections of a second or subsequent layer interconnection.
A still further object of the present invention is to provide a technique which is capable of performing a process for forming a second layer interconnection subsequently to a process for forming a capacitor requiring a high heat treating process and for using even a material which has a large thermal diffusion coefficient in the second layer interconnection.
A still further object of the present invention is to improve the quickness of response of a peripheral circuit or logic circuit formed on the same substrate as a DRAM having memory cells.
The above and other objects, and novel features of the present invention will become apparent from the description provided in the present specification and from the accompanying drawings.
Summaries of typical aspects of the invention disclosed in the present application will be described in brief as follows.
(1) A semiconductor integrated circuit device according to the present invention comprises memory cell selection MISFET
Fukuda Takuya
Kobayashi Nobuyoshi
Ohji Yuzuru
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Le Thao P.
Nelms David
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