Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-07
2002-08-06
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S067000
Reexamination Certificate
active
06429484
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices. More particularly, the present invention relates to a multiple active layer integrated circuit structure and a method of manufacturing such a structure. Even more specifically, the present invention relates to a semiconductor-on-insulator (SOI) multiple active layer integrated circuit and method of making such an integrated circuit.
BACKGROUND OF THE INVENTION
Semiconductor devices, such as, processors, non-volatile memory, and other circuits include semiconductor elements, such as, metal oxide semiconductor field effect transistors (MOSFETS), diodes, resistors, and capacitors. For example, flash memory devices employ millions of floating gate FETs and processors employ millions of complementary MOSFETS. MOSFETS are generally disposed in active regions disposed in a base layer or substrate. Active regions typically include heavily doped silicon or other semiconductor materials. The regions can be doped with impurities, such as, phosphorous (P), boron (B), arsenic (As), or other material.
Semiconductor elements, such as, floating gate transistors and FETS, are generally bulk semiconductor-type devices in contrast to semiconductor-on-insulator-type devices, such as, silicon-on-insulator (SOI) devices. The floating gate transistors and FETs are disposed in a single plane (single active layer) on a top surface of a semiconductor substrate, such as, a single crystal silicon substrate.
In bulk semiconductor-type devices which have lateral FETs, the top surface of the substrate is doped to form source and drain regions, and a conductive layer is provided on the top surface of the semiconductor substrate between the source and drain regions to operate as a gate. In floating gate FETS, the gate is provided over a floating gate. The number of layers of lateral FETs is limited to one layer (e.g., the top surface) because only one active region is available in conventional planar processes. Additionally, the anisotropic nature of the top surface of the silicon substrate due to the conductive layer limits the number of metal layers and insulative layers which can be provided over the lateral FETs. Thus, in bulk semiconductor-type devices, circuit density is limited by the integration density of electrical components on the surface of the wafer (substrate).
The use of only a single active layer can waste valuable silicon material. Bulk-type semiconductor devices utilizing multiple layers have been proposed to reduce the cost of integrated circuits and more efficiently utilize substrate area. These proposed devices utilize seeded epitaxial layers or recrystallized amorphous silicon layers to form multiple layers. For example, multiple active layer devices have been built using epitaxially-seeded lateral overgrowth (ESLO) techniques.
Bulk semiconductor-type devices can be subject to some disadvantageous properties, such as, less than ideal subthreshold voltage slope during operation, high junction capacitance, and ineffective isolation. Additionally, bulk semiconductor-type devices often require epilayers, P-wells, or N-wells which require additional fabrication steps.
Semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator) devices have significant advantages over bulk semiconductor-type devices, including near ideal subthreshold voltage slope, elimination of latch-up, low junction capacitance, and effective isolation between devices. SOI-type devices generally completely surround a silicon or other semiconductor substrate with an insulator and are a promising integration technology for sub-100 nm CMOS devices.
Devices, such as, conventional FETs or other transistors, are disposed on the silicon by doping source and drain regions and by providing gate conductors between the source and drain regions. The silicon is typically a very thin film (a silicon layer) separated from a bulk substrate or a support substrate by a thick buried oxide layer (a silicon dioxide layer). SOI devices provide significant advantages, including reduced chip size or increased chip density because minimal device separation is needed due to the surrounding insulating layers. Additionally, SOI devices can operate at increased speeds due to reduction in parasitic capacitance. These advantages are particularly important as integration technologies reach sub-100 nanometer levels for CMOS devices.
Conventional SOI devices generally have a floating substrate (the substrate is often totally isolated by insulating layers). Accordingly, SOI devices are subject to floating substrate effects, including current and voltage kinks, thermal degradation and large threshold voltage variations. SOI devices also can have some limited packing densities because they are limited in vertical integration. Generally, SOI devices can include a very thin (200-800 Å thick) silicon (Si) film separated from a bulk substrate by a thick buried silicon dioxide (SiO
2
) layer (2000-3000 Å thick). However, the thin silicon film is generally the only active layer.
SOI devices utilizing multiple layers have also been proposed. Multiple layers in these devices are achieved by stacking SOI wafers on top of each other. SOI wafers are often relatively thick and expensive (often 4 to 5 times as expensive as a bulk-type wafer). U.S. Pat. Nos. 5,889,302 and 5,936,280, issued to the assignee of the present application on Mar. 30, 1999 and Aug. 10, 1999, respectively, discuss a quadruple-gate field effect transistor on an SOI substrate. Quadruple-gate MOSFETS on multiple SOI wafers are utilized to increase vertical integration. Interlayer vias cross wafer boundaries to make connections between wafers.
Thus, there is a need for an SOI semiconductor device which has improved density and improved vertical integration. Further, there is a need for an SOI device which includes more than one active layer. Further still, there is a need for method of manufacturing an SOI device including more than one active layer. Yet further, there is a need for a multi-layer device which has some of the advantages of SOI devices without utilizing multiple SOI wafers.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to an integrated circuit. The integrated circuit includes a first semiconductor-on-insulator layer, a second active layer, and a second insulating layer. The semiconductor-on-insulator layer includes a first active layer and a first insulating layer. The first active layer contains a channel region and is disposed above the first insulating layer. The second active layer contains a second channel region. The second insulating layer is disposed. between the second active layer and the first active layer. The second insulating layer includes a seeding window.
Another exemplary embodiment relates to a multilayer structure for containing a plurality of transistors. The multilayer structure includes a first layer and a second active layer. The first layer includes an oxide layer, a first active semiconductor layer, and a first insulating layer. The oxide layer is disposed below the first active layer. The first active layer is disposed below the first insulating layer. The second active layer is disposed above the first insulating layer. The second active layer is recrystallized through a seeding window in the first insulating layer. At least one transistor is at least partially disposed in the first active layer and at least another transistor is at least partially disposed in the second active layer.
Yet another exemplary embodiment relates to a method of fabricating a multilayer structure for containing transistors. The method includes providing a first semiconductor-on-insulator substrate, providing a first insulating layer over the semiconductor-on-insulator substrate, and providing a seeding window in the first insulating layer. The method also includes forming a single crystalline semiconductor layer above the first insulating layer.
REFERENCES:
patent: 4272880 (1981-06-01), Pashley
patent: 4381201 (1983-04-01), Sakurai
patent: 4996574 (1991-02-01), Shirasaki
p
Advanced Micro Devices , Inc.
Foley & Lardner
Ngo Ngan V.
LandOfFree
Multiple active layer structure and a method of making such... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multiple active layer structure and a method of making such..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple active layer structure and a method of making such... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2912506