Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-23
2002-04-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S296000, C257S905000, C257S906000, C257S908000, C118S724000, C438S238000, C438S239000, C438S250000, C438S253000, C438S393000, C438S396000
Reexamination Certificate
active
06372639
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to processes for constructing conductive interconnects. More specifically, the present invention relates to processes for constructing a plurality of conductive interconnects on sub-micron semiconductor devices.
2. The Relevant Technology
Integrated circuits are manufactured by an elaborate process in which a variety of different microelectronic devices are integrally formed on a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) structure. In advanced manufacturing of integrated circuits, hundreds of thousands of electronic devices can be formed on a single substrate.
One of the steps in the fabrication of integrated circuits is to form generally horizontal conducting, e.g., metallic, interconnection or wire lines between the discrete microelectronic devices on the integrated circuit and to external circuitry. The horizontal interconnections are conducting layers that permit an electrical current to be delivered to and from the various microelectronic devices so that the integrated circuit can perform its intended function. Since the integrated circuitry needed for a semiconductor is usually build-up three-dimensionally on the substrate in order to increase the packing density and so forth, multilevel metallizations or conductors are generally necessary and employed. It will be appreciated that this necessitates the provision of inter-level dielectric layers interposed between different conductor levels formed on the device substrate.
Vias, also referred to as “vertical interconnects” or simply “interconnects,” are used to electrically connect different horizontal levels of metallization or conductors. The interconnect is a via hole or through hole filled with a conductor material that extends through a dielectric interposed between surfaces of two separate horizontal conductor levels. It will be appreciated that the layering process is repeated as needed to form additional levels and to form a plurality of similar horizontal and vertical conductive interconnections. Among other things, the yield, performance and reliability of the semiconductor device depend to a large extent on the accuracy of placement of the through hole with respect to the active regions of the individual semiconductor devices.
U.S. Pat. No. 5,869,403, which patent is incorporated herein by reference for all purposes, discloses formation of contact openings over a substrate in which an interconnect, e.g., a conducting polysilicon plug can be formed. Since many layers of material overlie the substrate, forming a desired contact opening necessarily involves etching through different overlying layers of material.
Referring to
FIGS. 1-3
, a semiconductor wafer fragment is shown generally at
10
. Fragment
10
includes a top surface
12
atop which two laterally spaced apart conductive lines
14
are formed. Lines
14
comprise respective polysilicon layers
16
, silicide layers
18
, and insulative nitride caps
20
, all of which having been formed by a previous anisotropic etch. Lines
14
also include insulative sidewall spacers
22
. It will also be appreciated that the lines
14
can be fabricated over a thin oxide layer
23
. However, since such details are well known to one of ordinary skill in the art, and since the presence or absence of such well known structure has no impact on either the art discussed in this section or the invention discussed below, fine details are omitted unless critical to understanding the present invention. It should also be noted that conductive lines
14
may form gates of transistor structures and that doped regions may be present in the silicon substrate
15
on either side of conductive line
14
. A thin oxide layer
24
is typically formed over the substrate and conductive lines
14
, and typically is composed of an oxide formed from decomposition of tetraethyloxysilane (TEOS). A layer
26
of borophosphosilicate glass (BPSG) is typically formed over layer
24
as shown.
FIG. 2
illustrate one possible problem associated with forming a contact opening to wafer or substrate
10
, wherein a contact opening
28
is anisotropically etched between conductive lines
14
to a degree sufficient to expose an area
30
of the substrate between the conductive lines and to which electrical connection is to be made. As the conductive lines
14
are pushed closer together, etching to surface
30
may also produce destructive etching of one or more layers associated with conductive lines
14
. It will be appreciated that this problem occurs more often as the device density increases. Typical etch chemistries for etching contact opening
28
etch BPSG layer
26
at a much faster rate than TEOS layer
24
. Accordingly, when the anisotropic etch reaches TEOS layer
24
between contact lines
14
(FIG.
1
), the etch must be conducted for a longer period of time to thereby ensure that TEOS layer
24
is completely removed to adequately expose area
30
. This etch, due in part to the differing etch rates between TEOS layer
24
and BPSG layer
26
, can overetch the inner-most side wall spacers
22
and erode nitride cap
20
thereby undesirably exposing silicide
18
as shown for the right-most conductive line
14
in FIG.
2
. The resulting condition can, and does, cause shorting between adjacent lines or devices when a polysilicon plug is formed in the etched area, thereby rendering the device useless.
FIG. 3
illustrates one proposed solution to the above-described problem, wherein contact opening
28
is made to be narrower between conductive lines
14
. As shown, the sides of contact opening
28
coincide with inner-most side wall spacers
22
so that the risk of overetching the side wall spacers and hence nitride caps
20
and silicide
18
is reduced. However, limiting the contact opening width, with the reduced risk of overetching, places severe constraints on the photomask and the alignment processes used to define contact opening
28
. It also produces a high aspect ratio (height to width of the etched area) which is harder to later fill with a conductor.
Another semiconductor wafer fragment is indicated generally by reference numeral
32
in
FIG. 4
, which is provided to illustrate an alternative method of producing interconnect vias. The fragment
32
includes a substrate
34
having a top surface
36
. A pair of conductive lines
38
are formed atop surface
36
and over substrate
34
by patterning and etching respective layers of polysilicon
40
, silicide
42
and nitride
44
. Nitride layers
44
form protective caps over the conductive lines. Sidewall spacers
46
, preferably also formed from nitride, are formed over conductive lines
38
and together with nitride caps
44
form a protective encapsulating layer. Conductive lines
38
constitute a pair of nitride insulated conductive lines between which electrical connection to substrate
34
is to be made. It will be noted that lines
38
are formed adjacent a substrate contact area
48
with which the electrical connection will be made.
A first oxide layer
50
is formed over substrate
34
and between conductive lines
38
covering at least part and preferably all of contact area
48
. In the illustrated and preferred example, layer
50
is an undoped oxide layer which is formed or deposited by decomposition of TEOS to a thickness of from about 300-500 Angstroms. A second oxide layer
52
is formed over first oxide layer
50
and is preferably formed from a different oxide material than layer
50
. It should be noted that second oxide layer
52
comprises a doped oxide layer of BPSG, which is formed or deposited over first layer
50
to a thickness of about 10,000-14,000 Angstroms. Thus, first oxide layer
50
is interposed between the substrate and second oxide layer
52
, i.e., directly beneath the second oxide layer.
FIG. 4
broadly illustrates the resultant semiconductor wafer fragment following a semiconductor processing method wherein a first oxide layer
50
is formed over the substrate to cov
Bowers Charles
Dickstein , Shapiro, Morin & Oshinsky, LLP
Kilday Lisa
Micro)n Technology, Inc.
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