Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-09-20
2002-08-13
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S207000, C365S185200, C365S185210
Reexamination Certificate
active
06434068
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory and, more particularly, to a nonvolatile semiconductor memory equipped with a testing circuit.
Referring to
FIG. 19
, the descriptions will be given of the operation performed by a conventional nonvolatile semiconductor memory if, for example, a defect, such as a short circuit or the like between a word line and a bit line, has led to a leakage current (constant current) of a cell current level from a bit line BL to a ground line.
The axis of abscissa of the characteristic curve shown in
FIG. 19
indicates a control gate voltage Vcg of a nonvolatile data storage memory cell (hereinafter referred to simply as “memory cell”), and the axis of ordinates indicates a drain current Ids of the memory cell. The descriptions will be given of a case where a power-supply voltage Vcc is employed as the control gate voltage Vcg.
Solid line (
1
) shown in
FIG. 19
ideally indicates the drain current Ids of the memory cell in state “1”, solid line (
2
) ideally indicates the drain current Ids of the memory cell in state “0”, and dashed line (
3
) ideally indicates a judgement reference current, namely, the drain current Ids of a reference cell.
If a leakage current is generated, then solid line (
1
) shifts to solid line (
1
)′, and solid line (
2
) shifts to solid line (
2
)′. A minimum operating voltage Vccmin and a maximum operating voltage Vccmax of data reading of the memory cell in state “0” will be an intersection “a” and an intersection “b”, respectively, of dashed line (
3
) and solid line (
2
)′.
In a test mode, a testing word line is set to an H-level to select a testing cell row, and normal word lines are set to an L-level to set the remaining memory cells to non-selection. Stored data is read out of a testing cell to determine “1”/“0” of the data.
If the testing cell is in state “1,” then a differential amplifier amp determines that the data is “1” on the basis of dashed line (
3
) indicating the judgment reference current, and outputs a voltage Vout of a level based on the determination result.
If the testing cell is in state “0,” and if the control gate voltage Vcg is the X-coordinate or more of the intersection “b” of dashed line (
3
) and solid line (
2
)′, or the X-coordinate or less of the intersection “a”, then the differential amplifier determines that the data is “1” and outputs the voltage Vout of the level based on the determination result.
Thus, such a defect involving a leakage current that is present in a bit line can be detected by selecting the testing cell row in the test mode.
To detect a defect in which a threshold voltage Vt of a reference cell is higher than a predetermined value, data is written to the testing cell to set it to a state “0.” Thereafter, the test mode is engaged, and a testing column decode signal and a word line are set to the H-level. By measuring a low-voltage operating voltage margin on a selected testing cell and the reference cell, it is possible to determine, on a cell in the state “0” whether the margin of the control gate voltage Vcg in a reading operation is insufficient.
As described above, a conventional one time programmable read-only memory (OTP) is equipped with a testing cell row and a reference column, and permits screening to be implemented for finding defective cells without the need for writing data to cells even after the OTP has been assembled.
The conventional OTP, however, has been equipped with a testing circuit unnecessary for normal operation for the testing cell row and the reference cell column. With the increasing trend toward further miniaturization of circuits typically represented by thinner wiring layers and smaller pitches between wires, the subdivision of bit lines and word lines are being enhanced. A testing cell has to be inserted on the basis of the minimum unit of divided memory cells. Therefore, the number of the testing cells is markedly increased, resulting in an increased proportion of a memory cell area in a total circuit area. This has been partly responsible for the difficulties in achieving a reduced scale of a completed device.
Furthermore, according to a conventional circuit configuration, it has been necessary to change the state “1”/“0” of a memory cell to carry out testing. This has been limiting the flexibility of a testing flow, and inevitably prolonging a test time because of the time required for writing data to a testing memory cell.
SUMMARY OF THE INVENTION
The present invention has been made with a view toward solving the problems described above. It is an object of the present invention to provide a nonvolatile semiconductor memory equipped with a testing circuit that permits the test of a current judgment memory cell and the leakage current screening on bit lines in a state wherein no data has been written.
A semiconductor memory circuit of the present invention comprises a word line, a bit line, a memory cell transistor having a first terminal applied to a first electrical potential, a second terminal connected to said bit line and a gate connected to the word line, a reference bit line, a reference cell transistor having a first terminal applied to the first electrical potential, a second terminal connected to the reference bit line and a gate connected to the word line, a sense node electrically connected to the bit line, a reference node electrically connected to the reference bit line, a differential amplifier having a first input connected to the sense node, a second input connected to the reference node and an output, a first load circuit connected between the sense node and a second potential source, a second load circuit connected between the reference node and the second potential source and a test circuit receiving a test signal. The first load circuit has a first resistance value. The second load circuit having a second resistance value that is lower than the first resistance value. The test circuit changes the first and second resistance values in response to the test signal.
REFERENCES:
patent: 5450354 (1995-09-01), Sawada et al.
patent: 5517448 (1996-05-01), Liu
patent: 5625591 (1997-04-01), Kato et al.
patent: 5748538 (1998-05-01), Lee et al.
patent: 5886937 (1999-03-01), Jang
patent: 5889702 (1999-03-01), Gaultier et al.
patent: 61180999 (1986-08-01), None
patent: 61181000 (1986-08-01), None
patent: 02210694 (1990-08-01), None
patent: 06-318683 (1994-11-01), None
Harada Teruhiro
Takeda Keichiro
Hoang Huan
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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