Method of fabricating a salicide of an embedded memory

Details Method of fabricating a salicide of an embedded memory Method of fabricating a salicide of an embedded memory

2001-04-18

2002-07-02

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S647000, C438S663000, C438S651000, C438S664000, C438S648000, C438S684000, C438S216000

Reexamination Certificate

active

06413861

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a self-aligned silicide (salicide) of an embedded memory.
2. Description of the Prior Art
Dynamic random access memory comprises a memory array region and a logic circuit region. With increasing integration, the present trend of manufacturing semiconductor integrated circuits is to integrate memory array region and high-speed logic circuit elements into a single chip. An embedded memory with both the integration of the memory array region and the logic circuits, significantly reduces the circuit area and increases the signal processing speed.
Please refer to
FIG. 1
to FIG.
6
.
FIG. 1
to
FIG. 6
are schematic diagrams of a method for fabricating silicide layers
22
and
44
of an embedded memory according to the prior art. As shown in
FIG. 1
, a semiconductor wafer
10
comprising a substrate
12
, a memory array region
14
and a periphery circuit region
16
defined on the substrate
12
is provided. The memory array region
14
performs data storage and the periphery circuit region
16
controls logic circuits. A plurality of shallow trench isolation (STI) structures
17
is positioned within the substrate
12
to isolate the elements.
At the first step of the prior method, a thermal oxidation process is performed to grow a dielectric layer of silicon dioxide on the substrate
12
, functioning as a gate oxide layer
18
. Then, a chemical vapor deposition (CVD) process is performed to deposit a doped polysilicon layer
20
, a silicide layer
22
and a cap layer
24
of silicon nitride, respectively, on the gate oxide layer
18
. Subsequently, a photoresist layer
26
is formed on the cap layer
26
followed by the use of a lithographic process to pattern the photoresist layer
26
and thus define the positions for forming gates.
As shown in
FIG. 2
, using the patterned photoresist layer
26
as a mask layer, a dry etching process is performed to remove the cap layer
24
, silicide layer
22
and polysilicide layer
20
down to the surface of the gate oxide layer
18
. Thereafter, as shown in
FIG. 3
, the photoresist layer
26
is completely removed, and a plurality of gates
28
is formed on the substrate
12
in the memory array region
14
, while a plurality of gates
30
is formed on the substrate
12
in the periphery circuit region
16
simultaneously. Therein, the silicide layer
22
combines with the doped polysilicon layer
20
to form a polycide layer as a primary conductive layer for each gate
28
and
30
. Following this, another photoresist layer is formed to cover the memory array region
14
. An ion implantation process is thereafter performed to simply form a doped area (not shown) on the substrate
12
adjacent to the gate
30
in the periphery circuit region
16
. After the photoresist layer is removed, a rapid thermal processing (RTP) is employed, such as to drive dopants in the doped area into the substrate
12
, to form a lightly doped drain (LDD)
32
in each MOS transistor in the periphery circuit region
16
.
As shown in
FIG. 4
, a silicon nitride layer (not shown) is deposited on the surface of the semiconductor wafer
10
. An anisotropic etching process is performed to etch back a portion of the silicon nitride layer and thus form spacers
34
and
36
on opposite sides of the gates
28
and
30
, respectively. Then, as shown in
FIG. 5
, a photoresist layer
38
is formed to cover all the gates
28
in the memory array region
14
. An ion implantation process is performed to implant the substrate
12
not covered by the photoresist layer
38
in the periphery circuit region
16
. As a result, a doped area (not shown) is formed on the substrate
12
in opposite sides of each gate
30
. Thereafter, another rapid thermal processing is used to drive dopants in the doped area into the substrate
12
, thus producing a source and a drain
40
for each MOS transistor in the periphery circuit region
16
.
As shown in
FIG. 6
, a dielectric layer
42
is formed on the surface of the substrate
12
in the memory array region
14
. Then, using the dielectric layer
42
as a mask, a salicide process is performed to simply form a salicide layer
44
on the surfaces of the source and drain
40
in the periphery circuit region
16
. Therein, the salicide process comprises: sputtering a titanium (Ti) layer (not shown) of 200 to 500 angstroms (Å) on the total surface of the substrate
12
, followed by the use of a RTP process to react the titanium layer with the silicon surface of the source and drain
40
, and thus forming the salicide layer
44
of titanium silicide.
In order to integrate a gate process in both the memory array region
14
and the periphery circuit region
16
, the prior method uses a polycide layer as a primary conductive layer for the gate
28
and
30
. The polycide layer prevents resistance of the gate from increasing, while increasing the ICs integration and shrinking the line width of gate. In addition, in order to improve the electrical performance of the elements in the periphery circuit region
16
, a salicide process is used to form the salicide layer
44
on the surfaces of the source and drain
40
. However, the polycide layer formed by a deposition process has a higher resistance, and thus is less ideal for improving the electrical performance of the periphery circuit region
16
. On the other hand, in order to reduce gate resistance and current leakage effectively, two salicide processes are used. As a result, a salicide layer as a conductive layer for each gate in both the memory array region
14
and the periphery circuit region
16
, is formed by the first salicide process. Another salicide layer on the source and drain
40
in the periphery circuit region
16
is thereafter formed by the second salicide process. However, using two salicide processes not only increases production cost but also wastes the thermal budget for the fabrication of an embedded memory.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of fabricating a salicide to improve the electrical performance of an embedded memory.
It is another objective of the present invention to provide a method of fabricating a salicide to decrease both production costs and wastage of thermal budget.
According to the claimed invention, a semiconductor wafer with a memory array region and a periphery circuit region defined on a silicon substrate of the semiconductor wafer is provided. A plurality of gates is also formed on the silicon substrate in both the memory array region and the periphery circuit region. Then, a barrier layer is formed on the total surface of the semiconductor wafer and covers each gate in both the memory array region and the periphery circuit region. Subsequently, a dielectric layer is formed on the barrier layer and fills a space between two gates. Using the barrier layer atop each gate in both the memory array region and the periphery circuit region as an end-point, a chemical mechanical polishing (CMP) process is thereafter performed to remove the dielectric layer atop the gates. After the CMP process, the surface of the remaining dielectric layer positioned between two gates is aligned with top surfaces of the gates. Following this, a lithographic process is performed to define a position for forming the salicide layer with a photoresist layer covering the memory array region and portions of the periphery circuit region. Using the photoresist layer as a mask, an etching process is performed to remove the dielectric layer and the barrier layer to expose the silicon substrate that is used to form the salicide layer. Finally, after the photoresist layer and the barrier layer atop each gate in the memory array region are removed, a salicide process is performed. As a result, a salicide layer is formed atop each gate and the substrate surface adjacent to the gates in the periphery circuit region, and another salicide layer is formed atop each gate in the memory array region simultaneo

Affiliated with

Also associated with

Rating

Method of fabricating a salicide of an embedded memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a salicide of an embedded memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a salicide of an embedded memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2911441