High voltage trigger remote-cathode SCR

Details High voltage trigger remote-cathode SCR High voltage trigger remote-cathode SCR

2000-10-26

2002-04-02

Lebentritt, Michael S. (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000, C257S357000, C257S362000, C257S363000

Reexamination Certificate

active

06365940

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of power devices, and more particularly to ESD protection in power devices.
BACKGROUND OF THE INVENTION
Current technology trends continue to focus on high performance CMOS (complementary metal-oxide-semiconductor) and a new arena of VLSI (very-large-scale integration) called Smart Power chips. Smart Power chips are built with both low and high voltage CMOS. Power transistors on these Smart Power chips typically allow operating voltages up to 40 volts. The thrust of current research focuses on improving the transistor performance.
Smart Power chips are widely used in the automotive industry. The automotive environment is harsh and requires relatively high levels of protection against ESD and other types of transients. However, power transistors are generally weak for ESD due to their inherent device structure. Good ESD performance actually requires low power dissipation capability under high currents. This is inherent in optimized nMOS transistor structures, but not in power transistors due to the fact that the holding voltages are quite high. A high holding voltage increases the relative power dissipation under an ESD event and results in a low self-protection level.
An example of a heretofore known DEnMOS power transistor is shown in FIG.
1
. The DEnMOS is built in a p-tank
112
located in a p-type epitaxial substrate
110
. The drain contact region
116
is formed in a n-well drain
114
. The source
118
is formed directly in the p-tank
112
. The gate
120
is located partially over the p-tank and partially over a field oxide region
122
that is located between the drain
116
and the source
118
. A 500 Å gate oxide
122
is located between the gate
120
and the p-tank
112
. Typically channel lengths (between the source
118
edge and the n-well
114
edge) are 3-4 &mgr;m. Smaller than 3 &mgr;m channel lengths are not used because the breakdown voltage (BVd
ss
) would be lowered for high voltage applications. Under high voltage conditions, the gate oxide region
122
does not breakdown since part of the voltage is supported by the depletion in the n-well
114
.
Proper ESD protection suitable for high voltage applications is often difficult to achieve. SCR's with high trigger voltage ranges can be designed but they are unacceptable for high voltage pins where a load dump (i.e., a transient voltage much greater than the maximum operating voltage of the system) is a threat in the automotive environment.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen in the art for improved ESD protection devices. The present invention provides a high voltage ESD protection device that substantially reduces or eliminates damage associated with ESD for high voltage applications.
In accordance with the present invention, a high voltage ESD protection device comprises a drain extended MOS transistor (DEnMOS) located in a tank region of a first conductivity type, a silicon controlled rectifier (SCR) merged with the DEnMOS into the tank region, and a resistor merged with the DEnMOS into the tank region. Different embodiments of the device can be provided where the first and second conductivity types are alternatively either p-type or n-type.
The DEnMOS transistor can include a first well region of a second conductivity type opposite the first conductivity type located in the tank, a drain of the second conductivity type located in the first well region, a source region of the second conductivity type located in the tank, a field oxide region in the tank separating the source from the first well, and a gate extending at least partially over the field oxide region. The gate and the source can be electrically connected to a ground potential.
The SCR can include a second well region of the second conductivity type located in the tank region, and an anode region of the first conductivity type also located in the second well region. The anode region can be electrically connected to a pad for providing ESD protection. In addition, an optional SCR diffusion region can be located within the second well region to provide latchup immunity. The SCR diffusion region can be of the same conductivity type as the second well region, and would be electrically connected to the anode.
The resistor can include a third well region of the second conductivity type and is also located in the tank region. Within the third well region, the resistor includes two resistor diffusion regions, one of which is electrically connected to the drain and the other electrically connected to the pad.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, descriptions, and claims.


REFERENCES:
patent: 5012317 (1991-04-01), Rountre
patent: 5225702 (1993-07-01), Chatterjee
patent: 5502317 (1996-03-01), Duvvury
patent: 5517051 (1996-05-01), Chatterjee
patent: 5604369 (1997-02-01), Duvvury et al.
patent: 5869873 (1999-02-01), Yu
patent: 5903032 (1999-05-01), Duvvury
patent: 5907462 (1999-05-01), Chatterjee et al.
patent: 5925922 (1999-07-01), Rountree et al.
patent: 5977596 (1999-11-01), Rountree et al.

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