Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-10-04
2002-08-13
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S253000, C438S396000, C438S722000
Reexamination Certificate
active
06432835
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device with a ferroelectric (high dielectric) capacitor and a fabrication process thereof, particularly, a process for forming a conductive material, which constitutes a lower electrode of the capacitor, at a high aspect ratio or high anisotropy.
Japanese Patent Application, Laid-Open No. HEI 10-98162 (Yunogami, et al.), described a technique developed with a view to forming a minute pattern with high dimensional accuracy without leaving a byproduct of low vapor pressure on the sidewall. Patterning a thin film such as Pt is by dry etching through a resist mask to form, on a sidewall of a thin film pattern, a positive taper reaching its lower end, with a photoresist of a predetermined pattern as a mask. The photoresist has a substantially vertical sidewall at least at the lower half and a positive taper or rounding at the outer periphery of the top portion.
Japanese Patent Application, Laid-Open No. Hei 9-205183 (Shibano), described a technique developed with a view to reducing generation of irregularities on the surface or sidewall of the ruthenium film after etching or etching residues and making the taper shape of the etching as vertical as possible, thereby forming a fine pattern. Etching a ruthenium film is by a mixed gas plasma containing chorine and oxygen, while regulating the total flow of the mixed gas so that a gas residence time in an etching chamber becomes 45 msec or less.
Japanese Patent Application, Laid-Open No. Hei 7-221197 (Kajiyana), described a technique developed with a view to preventing the use of a resist film as a mask. A ruthenium dioxide film is subjected to RIE (Reactive Ion Etching) by using an oxygen plasma and an oxygen plasma resistant film (SOG film, TiN film, TiSi film, polysilicon film, amorphous Si film, plasma SiN film, Al film or Cr film) as a mask.
Japanese Patent Application, Laid-Open No. 153707 (Tokashiki), described a technique developed with a view to removing, during the formation of fine patterns from platinum or a conductive oxide, the contamination on the surface of the patterns with carbon, a halogen member or the like. At the same time, the surface condition of an electrode is improved to equal or be much similar to the condition at the formation time of an electrode material. An electrode containing ruthenium, ruthenium oxide or the like is dry etched and then followed by treating the electrode surface with ozone, water vapor or nitrogen oxide gas.
Japanese Patent Application, Laid-Open No. Hei 5-267226 (Kumihashi, et al.), described a technique developed with a view toward improving the throughput upon time modulation etching. The residence time of a processing gas in a vacuum processing chamber is improved to 100 msec or less by using an evacuation pump having an effective exhaust speed of at least 1300 liter/s.
Japanese Patent Application, Laid-Open No. Hei 8-107105 (Tatsumi), described a technique developed with a view to preventing the generation of a residue upon patterning of a film including a of a silicone material such as polycrystalline silicone. A high selection ratio to an underlying insulation film is obtained by patterning the silicone material film on the insulation film through a first etching step of a high etching rate and a second etching step of a high selection ratio. An evacuation rate of an etching gas in the second etching step is set larger than in the first etching step, more specifically, at 1000 liter/sec.
Japanese Patent Application, Laid-Open No. Hei 7-7001 (Tomita, et al.), described a technique developed with a view to providing a plasma etching system or device permitting stable and continuous use for long hours by suppressing generation of a polymer of a processing gas stuck onto the peripheral wall of a gas exhaust nozzle. A gas supply is controlled so that the mass flow of a gas passing through a thin hole of a shower electrode becomes at least 620 kg/m
2
/hour.
Japanese Patent Application, Laid-Open No. Hei 5-267249 (Kumihashi, et al.), described a technique developed with a view to facilitating anisotropic etching and over etching. An effective exhaust speed in a vacuum processing chamber and/or a flow of a processing gas is changed from one condition forming a deposition film on the sidewall of the etching pattern of a sample to the condition of not forming or forming in the opposite order.
SUMMARY OF THE INVENTION
As a part of the present invention, the inventor has investigated a large capacity DRAM (Dynamic Random Access Memory) of at least 1 G bit, as a countermeasure to make up for a decrease of an accumulated charge amount occurring with the miniaturization of a memory cell. The capacitor insulating film of a capacitor for information storage was made from a high dielectric material such as Ta
2
O
5
having a relative dielectric constant of about 20 and having a non-Perovskite structure or BST ((Ba, Sr)TiO
3
) having a relative dielectric constant of at least 100 and being an ABO
3
type complex oxide, that is, a Perovskite type complex oxide, or a ferroelectric material, such as PZT (PbZr
x
Ti
1−x
O
3
), PLT(PbLa
x
Ti
1−x
O
3
), PLZT, PbTiO
3
, SrTiO
3
or BaTiO
3
, having a crystalline structure such as a Perovskite structure. Also in the field of a non-volatile memory, a ferro-electric memory making use of polarization inversion of the above-described ferro-electric material for the retention of memory is under development.
When the capacitor insulating film of a capacitor is formed of a ferro-electric material as exemplified above or where a ferro-electric material as exemplified above is employed as the polarization inversion film of a nonvolatile memory, electrode conductive films are formed having therebetween a ferroelectric material film. For example, they are formed from a metal including a platinum group member (ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) and platinum (Pt)) or an oxide thereof having high affinity with the above-described ferro-electric material, as described in the above literature.
In general, however, the above-exemplified platinum metal or oxide thereof cannot be etched with good anisotropy and there is a potential danger that inferior, short-circuits occur owing to an etching residue. For example, the formation of a capacitor by using Pt is accompanied with the problem that: upon dry etching of a Pt thin film deposited on a substrate, a large amount of a low vapor pressure byproduct sticks to a sidewall of the pattern, which becomes a cause of a short circuit between capacitors. The existence of such a byproduct sticking to the sidewall of a pattern also becomes a cause for deteriorating the anisotropy of the pattern.
According to the investigation by the present inventors, when a high dielectric BST is employed for a capacitor insulating film of a 1 G bit DRAM, a lower electrode desirably has a minimum width of 0.13 um and a height of 0.45 um, because a space of 0.13 um between adjacent lower electrodes is required. In order to form such a fine pattern while imparting it with sufficient reliability in practical use, a taper angle of at least 80 degrees, preferably at least 85 degrees, is preferred. The term taper angle as used herein means an angle formed between a sidewall of a lower electrode and the surface of a material below the lower electrode.
FIG. 42
is a cross-sectional view schematically illustrating the relation between a taper angle and a fine pattern shape. As illustrated in
FIG. 42
, a taper angle of 90 degrees is ideal. Supposing that a width of the bottom surface of the pattern is 0.13 um and a pattern height is 0.45 um, such a pattern height cannot be obtained at a taper angle of 80 degrees (FIG.
42
(
f
)). Such a pattern height is attained for the first time when the taper angle becomes 82 degrees (FIG.
42
(
e
)) which however does not secure an area on the upper surface of the pattern. When the taper angle is 85 degrees (FIG.
42
(
d
)), an area on the upper surface of the pattern is secured
Nojiri Kazuo
Yunogami Takashi
Fahmy Wael
Kebede Brook
Mattingly Stanger & Malur, P.C.
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