Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-24
2002-08-06
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S301000, C257S296000
Reexamination Certificate
active
06429478
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory device and a method of fabricating the same, and more particularly to a semiconductor memory device storing data by accumulating electric charges in a capacitor formed in the device, and a method of fabricating the same.
2. Description of the Related Art
A dynamic random access memory (DRAM) is one of memories comprises of a transistor and a capacitor.
FIGS. 1A
to
1
E are cross-sectional view of a cell in a conventional dynamic random access memory, each illustrating a step of a method of fabricating the same.
First, as illustrated in
FIG. 1A
, isolating regions
2
are formed at a surface of a semiconductor substrate
1
by the shallow trench isolation (STI) process. The adjacent isolation regions
2
define a region therebetween in which a transistor is to be fabricated.
Then, transistors (not illustrated) are fabricated between the isolation regions
2
, followed by ion-implantation to the semiconductor substrate
1
between the isolation regions
2
to thereby form diffusion layers
3
at a surface of the semiconductor substrate
1
.
Then, a first interlayer insulating film
4
is formed on the semiconductor substrate
1
. After planarization of the first interlayer insulating film
4
by chemical mechanical polishing (CMP), a photoresist film (not illustrated) is deposited on the first interlayer insulating film
4
. After patterning the photoresist film, the first interlayer insulating film
4
is etched with the patterned photoresist film being used as a mask, to thereby form contact holes
5
throughout the first interlayer insulating film
4
such that the contact holes
5
reach the diffusion layer
3
.
Then, polysilicon is grown entirely over the first interlayer insulating film
4
and the diffusion layer
3
, and thereafter, is etched back by dry etching. As a result, the polysilicon remains non-etched only in the contact holes
5
. The polysilicon remaining in the contact holes
5
defines first electrically conductive layers
6
acting as pads.
Then, as illustrated in
FIG. 1B
, an interlayer insulating film
7
is formed entirely over the second interlayer insulating film
4
and the first electrically conductive layers
6
. Then, there are formed contact holes (not illustrated) through both the interlayer insulating film
7
and the first interlayer insulating film
4
such that the contact holes connect later mentioned bit lines to a circuit (not illustrated) formed on the semiconductor substrate
1
.
Then, a tungsten polycide film is formed on the interlayer insulating film
7
. Then, the tungsten polycide film is patterned by photolithography and etching to thereby form bit lines
8
on the interlayer insulating film
7
.
Then, as illustrated in
FIG. 1C
, a second interlayer insulating film
9
is formed on the interlayer insulating film such that the bit line
8
are entirely covered with the second interlayer insulating film
9
. After planarizing the second interlayer insulating film
9
, contact holes
10
are formed throughout the second interlayer insulating film
9
by photolithography and etching such that the contact holes
10
reach the first electrically conductive layers
6
.
Then, the contact holes
10
are filled with polysilicon to thereby form plugs
11
in the contact holes
10
in the same manner as forming the first electrically conductive layers
6
.
Then, as illustrated in
FIG. 1D
, a third interlayer insulating film
12
is formed entirely over the second interlayer insulating film
9
and the plugs
11
. Then, the third interlayer insulating film
12
is patterned by photolithography and etching to thereby form recesses
13
throughout the third interlayer insulating film
12
such that the recesses
13
reach the plugs
11
.
Then, as illustrated in
FIG. 1E
, each of the recesses
13
is covered at its inner sidewall and bottom with a lower electrode
14
composed of polysilicon.
It is preferable for a capacitor to have a greater capacity for writing data thereinto or reading data therefrom. In order to enhance a capacity of a capacitor, each of the recesses
13
illustrated in
FIG. 1E
needs to have a greater surface area, that is, the lower electrode
14
needs to have a greater height. To this end, the third interlayer insulating film
12
needs to have a greater thickness.
However, if the third interlayer insulating film
12
is designed to have a greater thickness, the contact holes
5
,
10
and
13
reaching the circuit formed on the semiconductor substrate
1
have to have a greater depth, resulting in an increase in difficulty for fabricating the semiconductor memory device.
A memory used in a computer has been designed to have a greater capacity, and a cell in a semiconductor memory device has been designed to be fabricated in a smaller size. Accordingly, there is caused a problem that it is more and more difficult to stably pattern a photoresist film for forming the contact holes
10
in accordance with a minimum design rule.
For instance, Japanese Patent No. 2850833 (Japanese Unexamined Patent Publication No. 9-232427) has suggested a method of fabricating a semiconductor device, including the steps of forming a plurality of wirings on a semiconductor substrate, forming a sidewall layer around each of sidewalls of the wirings, forming an interlayer insulating film covering the wirings and the sidewall layers therewith, and etching both the interlayer insulating layer and the sidewall layers by making an etching rate of the sidewall layers equal to or greater than an etching rate of the interlayer insulating film, to thereby form contact holes between the wirings. Each of the sidewall layers is comprised of a silicon dioxide film into which impurity is doped, and a coat insulating film keeping the silicon dioxide film away from the semiconductor substrate by covering both sidewalls of the wirings and the semiconductor substrate therewith.
Japanese Unexamined Patent Publication No. 9-97902 has suggested a method of fabricating a semiconductor device, including the steps of forming a first wiring layer on a semiconductor substrate, a forming a first etching stopper film covering the first wiring layer therewith, forming a first interlayer insulating film over the first etching stopper film and the semiconductor substrate, forming a second wiring layer on the first interlayer insulating film, forming a second etching stopper film on the second wiring layer such that the second etching stopper film is horizontally more extensive than the second wiring layer and projects from a sidewall of the second wiring layer, forming a second interlayer insulating film on the semiconductor substrate, and forming a contact hole extending from a surface of the second interlayer insulating film to either a surface of the first etching stopper film or a surface of the semiconductor substrate. An etching mask formed on the second interlayer insulating film is composed of the same material as a material of which the second etching stopper film is composed.
Japanese Unexamined Patent Publication No. 9-321024 has suggested a method of fabricating a semiconductor device, including the steps of etching a silicon dioxide film relative to a silicon nitride film through the use of a first process gas containing phlorocarbon gas having no hydrogen bondings, and etching the silicon dioxide film relative to the silicon nitride film through the use of a second process gas containing CO gas and phlorocarbon gas having hydrogen bondings.
Japanese Unexamined Patent Publication No. 11-87653 has suggested a method of fabricating a semiconductor device, including the steps of forming a gate insulating film in active regions on a semiconductor substrate, forming a plurality of first gate electrodes in a first region and a plurality of second gate electrodes in a second region, the first gate electrodes having a high patterning density and the second gate electrodes having a low patterning density, forming source and drain regions in the semiconductor subs
Lebentritt Michael S.
Scully Scott Murphy & Presser
Smith Brad
LandOfFree
Semiconductor device which increases the capacity of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device which increases the capacity of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device which increases the capacity of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2910350